Makoto Noda

A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology

A 54 b*54 b multiplier fabricated in a double-metal 0.5 mu m CMOS technology is described. The 54 b*54 b full array is adopted to complete multiplication within one latency. A 10 ns multiplication time is achieved by optimizing both the propagation time of the part consisting of 4-2 compressors and the propagation time of the final adder part. The n-channel pass-transistor circuit and the p-channel load circuit are used at the critical blocks to improve the multiplication speed. This multiplier is intended to be applied to double-precision floating-point data processing based on the IEEE standard up to clock range of 100 MHz. >

A one-chip scalable 8*8 ATM switch LSI employing shared buffer architecture

The authors present a one-chip scalable 8*8 shared buffer switch LSI which includes a 256-cell buffer. Speedup, flow control, and input slot rotation functions are provided in order to interconnect LSIs for scaling-up without degrading cell loss rates. Computer simulations show that these functions bring a satisfactory result and can make the cell loss- rate for a Clos three-stage network superior to that for the output buffer switch which includes the same amount of buffer space. A 0.8 mu m BiCMOS process is employed for this LSI. The total number of transistors is one million. This LSI has already been fabricated. >

Simple expressions for interconnection delay, coupling and crosstalk in VLSI's

RC interconnection delay is one of the most essential issues in recent VLSIs. A closed-form formula for a waveform of the RC line with practical boundary conditions is derived. Expressions are also derived for a voltage slope and transition time of the RC interconnection. Other important issues related to interconnections are capacitive coupling of two lines and a crosstalk induced by the capacitive coupling. Expressions are derived for a coupling capacitance and a crosstalk voltage height, which can be used in VLSI designs. Using the expression, optimum line width which minimizes RC delay is discussed.<<ETX>>

A single-power-supply 10-b video BiCMOS sample-and-hold IC

A +5-V single-power-supply 10-b video BiCMOS sample-and-hold IC is described. Video speed, low power, and 10-b accuracy sample-and-hold operation have been achieved using a complementary connected buffer format sample switch. A high-speed p-n-p transistor used in the sample switch is formed by a combination of n-p-n and PMOS transistors. The sample-and-hold operation is accomplished by feeding back the hold capacitor voltage to the sample switch inputs, so that the inputs transfer symmetrically for the hold capacitor voltage at any input level. The sample-and-hold IC has been implemented in 1.2- mu m BiCMOS technology and evaluated. The following results have been obtained: 185-MHz 3-dB bandwidth at 22-pF hold capacitor, 63-dB signal-to-noise ratio at 8-MHz full-scale input, 20-ns acquisition time at 1-V step input, 15-ns switch setting time, and 0.1% linearity error. Power dissipation is 150 mW. >

0.5/spl mu/m 2M-transistor BipnMOS Channelless Gate Array

A channelless gate array has been realized using 0.5- mu m BiCMOS technology integrating more than two million transistors on a 14-mm*14.4-mm chip. A small-size PMOS transistor and a small-size inverter are added to the conventional BiNMOS gate to form the BiPNMOS gate. The gate is suitable for 3.3-V supply and achieves 230-ps gate delay for a two-input NAND with full-swing output. Added small-size MOS transistors in the BiPNMOS basic cell can also be used for memory macros effectively. A test chip with four memory macros-a high-speed RAM, a high-density RAM, a ROM, and a CAM macro-was fabricated. The high-speed memory macros utilize bipolar transistors in bipolar middle buffers and in sense amplifiers. The high-speed RAM macro achieves an access time of 2.7 ns at 16-kb capacity. The high-density RAM macro is rather slow but the memory cell occupies only a half of the BiPNMOS basic cell using a single-port memory cell. >

A 1.9 ns BiCMOS CAM macro with double match line architecture

A 64-entry*32-b high-speed BiCMOS CAM (content addressable memory) macro is implemented on a 0.5 mu m BiPNMOS sea-of-gates. In order to realize high-speed operation, a double match line (DML) architecture and a BiCMOS pull-up circuit are employed. The BiCMOS pull-up circuit imparts high drivability to a second match-line driver. A fabricated chip shows 1.9 ns of address-to-match delay time. The CAM macro also has high-density characteristics because a single CAM cell occupies only one basic cell of the gate array. Since the CAM macro is implemented on a gate array, the configuration can be altered easily and quickly depending on customers requests.<<ETX>>

1.65 Gb/s 60 mW 4:1 multiplexer and 1.8 Gb/s 80 mW 1:4 demultiplexer ICs using 2 V 3-level series-gating ECL circuits

The 1.65 Gb/s 60 mW 4:1 multiplexer and 1.8 Gb/s 80 mW 1:4 demultiplexer ICs in a 1.2 /spl mu/m, 15 GHz bipolar process operate with a -2 V single power supply, and exhibit the lowest power-delay products reported to date. Low dissipation results from ECL circuit techniques enabling three-level series gating with a 2 V supply.

A 350 ps 50 K 0.8 amu;m BiCMOS gate array with shared bipolar cell structure

A BiCMOS gate array with gate delay of 350 ps has been realized by 0.8-μm BiCMOS technology. Minimum gate delay and cell area have been achieved with a shared bipolar cell structure. The gate delay is almost equivalent to that of a 0.5-μm pure CMOS gate array. The cell-area increase is to only 25% compared with a 0.8-μm pure CMOS cell. I/O cells can interface with CMOS, TTL (transistor-transistor logic), and ECL (emitter-coupled logic) chips at the same time with a single supply voltage of 5 V

A 10 ns 54atimes;54-bit parallel structured full array multiplier with 0.5 amu;m CMOS technology

A 54-b&times;54-b multiplier fabricated in double metal 0.5-&mu;m CMOS technology is described. A 10-ns multiplication time has been achieved by employing a 4-2 compressor, a carry select adder, and a carry lookahead adder. The 54-b&times;54-b full array is adopted to complete the multiplication within one latency. This multiplier is intended for double-precision floating-point data processing based on IEEE standards up to a clock range of 100 MHz. The multiplier has integrated 81600 transistors in an active area of 3.62 mm&times;3.45 mm

A 5 ns 369 kb port-configurable embedded SRAM with 0.5 mu m CMOS gate array

An SRAM that has column-sliceable peripheral circuitry embedded in a 235 K CMOS gate array and improved flexibility in configuration is described. The port-configurable (PC) SRAM cell achieves the minimum area overhead associated with the configurability by using four port-customization terminals at every memory-cell boundary. Prior to customization, first and second polysilicon are used to connect the internal memory-cell nodes to the port-customization terminals. Multiport SRAMs are configured by first Al so that corresponding internal nodes of adjacent memory cells are connected. At the same time, word lines are configured according to the port customization using second Al and the via hole. The use of second Al is a key to the density and speed. A high-resistance polysilicon load cell is used to provide good write operation and high density. The cell size is 9*13.6 mu m, one-tenth the area of an equivalent multiport cell based on gate-array basic cells. The worst-case access speed of multiport configuration based on this scheme has no dependence on the number of ports because the memory-cell current available to drive unit bit-line load capacitance remains constant. In the multiport configuration, the write operation from one port must flip all of the connecting cells through the NMOS transfer gate of the write port cell. Therefore, a six-transistor full CMOS SRAM cell is not suitable for PC SRAM.<<ETX>>