Maitreyee Mahajani

High-k Gate Stack: Improved Reliability through Process Clustering

Introduction High-k (HK) gate dielectric stack process integration is one of the most critical and challenging steps in the fabrication of CMOS since its adoption at the 45nm node [1]. A typical HK stack consists of the SiO2 interfacial layer (iL) followed by a nitrided and annealed HK dielectric. Both the nitridation and anneal results in an increased dielectric constant and improved HK and stability. It has been demonstrated in numerous papers that the quality of the HK bulk material and the interface with the iL plays a critical role in transistor’s reliability degradation. This degradation, generally due to electron trapping in the HK bulk and/or at the iL/HK interface, is quantified by Bias-Temperature Instability (BTI) which closely correlates to CV hysteresis [2]. Because of such reliability degradation concerns, clustering of the different HK stack process chambers in one single tool is critical in eliminating layer exposure to fab ambient that could result in HK bulk and interface quality degradation.