Patricia M. Liu

A novel high-k gate dielectric HfLaO for next generation CMOS technology

The physical and electrical characteristics of high-k (HK) gate dielectric HfLaO were systematically investigated. Incorporation of La in HfO2 can raise the film crystallization temperature from 400degC to 900degC. Moreover, NMOSFETs fabricated with HfLaO gate dielectric exhibit superior electrical performances in terms of threshold voltage (Vth), bias temperature instability (BTI), channel electron mobility and gate leakage current compared to those fabricated with HfO2 dielectric. Particularly, the authors also report that the effective work function (EWF) of metal gate (MG) can be tuned to a wide enough range to fulfil the requirement of bulk CMOSFETs by employing HfLaO dielectric and n- and p-type metal gates respectively. These advantages are correlated to the enhanced thermal stability and reduction of oxygen vacancy density in HfLaO compared to HfO2, making it a promising high-k gate dielectric to replace SiO2 and SiON to meet the ITRS requirements. Finally, a possible dual metal gate CMOS integration process is proposed

The effect of interfacial oxide and high-κ thickness on NMOS V th shift from plasma-induced damage

Different thicknesses of interfacial oxide and high-κ were used to study the effects of plasma-induced damage (PID) in NMOS transistors. The thickness of high-κ HfO₂ was varied from 15Å to 25Å. The thickness of the interfacial layer (IL) with N₂O/H₂ was also varied from 5Å to 10Å. The threshold voltage (V_th) shift was observed to be greater in the thinner oxide using the same plasma condition. There was no significant effect with different IL thickness between 5Å and 10Å.

High-k Gate Stack: Improved Reliability through Process Clustering

Introduction High-k (HK) gate dielectric stack process integration is one of the most critical and challenging steps in the fabrication of CMOS since its adoption at the 45nm node [1]. A typical HK stack consists of the SiO2 interfacial layer (iL) followed by a nitrided and annealed HK dielectric. Both the nitridation and anneal results in an increased dielectric constant and improved HK and stability. It has been demonstrated in numerous papers that the quality of the HK bulk material and the interface with the iL plays a critical role in transistor’s reliability degradation. This degradation, generally due to electron trapping in the HK bulk and/or at the iL/HK interface, is quantified by Bias-Temperature Instability (BTI) which closely correlates to CV hysteresis [2]. Because of such reliability degradation concerns, clustering of the different HK stack process chambers in one single tool is critical in eliminating layer exposure to fab ambient that could result in HK bulk and interface quality degradation.