Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Mamoru Fujita is active.

Publication


Featured researches published by Mamoru Fujita.


international solid-state circuits conference | 1996

A 2.5 ns clock access 250 MHz 256 Mb SDRAM with a synchronous mirror delay

Takanori Saeki; Y. Nakaoka; Mamoru Fujita; Akio Tanaka; K. Nagata; K. Sakakibara; Tatsuya Matano; Y. Hoshino; K. Miyano; Satoshi Isa; S. Nakazawa; E. Kakehashi; J.M. Drynan; M. Komuro; T. Fukase; Haruo Iwasaki; M. Takenaka; J. Sekine; M. Igeta; N. Nakanishi; Toshiro Itani; I. Yoshida; K. Yoshino; S. Hashimoto; T. Yoshii; M. Ichinose; T. Imura; M. Uziie; S. Kikuchi; Kuniaki Koyama

A 245.7 mm/sup 2/ 256 Mb SDRAM uses: (1) 60.2% cell-occupancy ratio array, (2) prefetched pipeline using first-in first-out buffer with parallel/serial converter, (3) synchronous mirror delay circuit.


international solid-state circuits conference | 1993

A 30-ns 256-Mb DRAM with a multidivided array structure

Tadahiko Sugibayashi; Toshio Takeshima; Isao Naritake; T. Matano; Hiroshi Takada; Yoshiharu Aimoto; Koichiro Furuta; Mamoru Fujita; Takanori Saeki; Hiroshi Sugawara; Tatsunori Murotani; Naoki Kasai; Kentaro Shibahara; K. Nakajima; Hiromitsu Hada; Takehiko Hamada; Naoaki Aizaki; T. Kunio; E. Kakehashi; K. Masumori; Takaho Tanigawa

A 256-Mb DRAM with a multidivided array structure has been developed and fabricated with 0.25- mu m CMOS technology. It features 30-ns access time, 16-b I/Os, and a 35-mA operating current at a 60-ns cycle time. Three key circuit technologies were used in its design: a partial cell array activation scheme for reducing power-line voltage bounce and operating current, a selective pull-up data-line architecture to increase I/O width and reduce power dissipation, and a time-sharing refresh scheme to maintain the conventional refresh period without reducing operational margin. Memory cell size was 0.72 mu m/sup 2/. Use of the trench isolated cell transistor and the HSG cylindrical stacked capacitor cells helped reduce chip size to 333 mm/sup 2/. >


Archive | 1993

Dynamic random access memory device having sense amplifier arrays selectively activated when associated memory cell sub-arrays are accessed

Tadahiko Sugibayashi; Mamoru Fujita; Isao Naritake


Archive | 1996

High speed semiconductor memory with burst mode

Mamoru Fujita


Archive | 1993

Semiconductor memory device having dual word line structure

Mamoru Fujita


Archive | 1999

Synchronous semiconductor memory device having burst access mode and multi-bit pre-fetch operation

Mamoru Fujita


international solid-state circuits conference | 1999

A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme

Yasuhiro Takai; Mamoru Fujita; K. Nagata; Satoshi Isa; S. Nakazawa; A. Hirobe; Hiroaki Ohkubo; Masato Sakao; S. Horiba; T. Fukase; Y. Takaishi; M. Matsuo; M. Komuro; T. Uchida; T. Sakoh; K. Saino; S. Uchiyama; Y. Takada; J. Sekine; N. Nakanishi; T. Oikawa; M. Igeta; Hiroshi Tanabe; Hidenobu Miyamoto; Takasuke Hashimoto; Hiroshi Yamaguchi; Kuniaki Koyama; Y. Kobayashi; Takashi Okuda


Archive | 1999

Semiconductor memory having signal input circuit of synchronous type

Mamoru Fujita


Archive | 1996

Synchronous semiconductor memory having a burst transfer mode with a plurality of subarrays accessible in parallel via an input buffer

Mamoru Fujita


Archive | 1995

Semiconductor memory having redundancy memory decoder circuit

Satoshi Isa; Mamoru Fujita

Researchain Logo
Decentralizing Knowledge