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Dive into the research topics where Tatsuya Matano is active.

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Featured researches published by Tatsuya Matano.


international solid-state circuits conference | 1996

A 2.5 ns clock access 250 MHz 256 Mb SDRAM with a synchronous mirror delay

Takanori Saeki; Y. Nakaoka; Mamoru Fujita; Akio Tanaka; K. Nagata; K. Sakakibara; Tatsuya Matano; Y. Hoshino; K. Miyano; Satoshi Isa; S. Nakazawa; E. Kakehashi; J.M. Drynan; M. Komuro; T. Fukase; Haruo Iwasaki; M. Takenaka; J. Sekine; M. Igeta; N. Nakanishi; Toshiro Itani; I. Yoshida; K. Yoshino; S. Hashimoto; T. Yoshii; M. Ichinose; T. Imura; M. Uziie; S. Kikuchi; Kuniaki Koyama

A 245.7 mm/sup 2/ 256 Mb SDRAM uses: (1) 60.2% cell-occupancy ratio array, (2) prefetched pipeline using first-in first-out buffer with parallel/serial converter, (3) synchronous mirror delay circuit.


Archive | 2001

Level converter circuit

Tatsuya Matano


Archive | 1996

Semiconductor memory device with reduced chip area

Tatsuya Matano


Archive | 2000

Semiconductor device with less influence of noise

Tatsuya Matano


Archive | 2001

Data processing circuit having a waiting mode

Tatsuya Matano


Archive | 1996

Synchronous DRAM performing refresh operation a plurality of times in response to each refresh request command

Tatsuya Matano


Archive | 1998

Semiconductor memory device with control for auxiliary word lines for memory cell selection

Tatsuya Matano


Archive | 1993

Dynamic random access memory device having precharge circuit for intermittently and selectively charging data line pairs

Tatsuya Matano; Tadahiko Sugibayashi; Hiroshi Takada


Archive | 2000

Semiconductor memory device equipped with voltage generator circuit

Tatsuya Matano


Archive | 1993

Double word line type dynamic RAM having redundant sub-array of cells

Tadahiko Sugibayashi; Isao Naritake; Tatsuya Matano

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