Tatsuya Matano
NEC
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Publication
Featured researches published by Tatsuya Matano.
international solid-state circuits conference | 1996
Takanori Saeki; Y. Nakaoka; Mamoru Fujita; Akio Tanaka; K. Nagata; K. Sakakibara; Tatsuya Matano; Y. Hoshino; K. Miyano; Satoshi Isa; S. Nakazawa; E. Kakehashi; J.M. Drynan; M. Komuro; T. Fukase; Haruo Iwasaki; M. Takenaka; J. Sekine; M. Igeta; N. Nakanishi; Toshiro Itani; I. Yoshida; K. Yoshino; S. Hashimoto; T. Yoshii; M. Ichinose; T. Imura; M. Uziie; S. Kikuchi; Kuniaki Koyama
A 245.7 mm/sup 2/ 256 Mb SDRAM uses: (1) 60.2% cell-occupancy ratio array, (2) prefetched pipeline using first-in first-out buffer with parallel/serial converter, (3) synchronous mirror delay circuit.
Archive | 2001
Tatsuya Matano
Archive | 1996
Tatsuya Matano
Archive | 2000
Tatsuya Matano
Archive | 2001
Tatsuya Matano
Archive | 1996
Tatsuya Matano
Archive | 1998
Tatsuya Matano
Archive | 1993
Tatsuya Matano; Tadahiko Sugibayashi; Hiroshi Takada
Archive | 2000
Tatsuya Matano
Archive | 1993
Tadahiko Sugibayashi; Isao Naritake; Tatsuya Matano