Kuniaki Koyama

A 2.5 ns clock access 250 MHz 256 Mb SDRAM with a synchronous mirror delay

A 245.7 mm/sup 2/ 256 Mb SDRAM uses: (1) 60.2% cell-occupancy ratio array, (2) prefetched pipeline using first-in first-out buffer with parallel/serial converter, (3) synchronous mirror delay circuit.

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

A 64 Mw*1 b/16 Mw*4 b DRAM with 30-ns access time which uses a double-metal layer and 0.4- mu m CMOS technology is reported. The external power supply is 3 V, while memory cell arrays operate at 2.2 V. Key circuits for the 64-Mb DRAM are (1) a latched-sense, shared-sense circuit with open bit-line read-out and folded bit-line rewrite operations (LOF) to reduce inter-bit-line coupling noise, (2) alternatively activated and separately end-located word drivers and X decoders to reduce word-line selection delay, and (3) built-in self test and repair circuits using spare memory cells to reduce test costs and increase chip reliability. >

A 1-Gb DRAM for file applications

A number of large capacity DRAMs have been developed recently for file applications because data storage devices play an important role in high-speed communication and graphic systems. Such file memories must have low power dissipation, high data transfer rate and low cost. A low chip-yield problem is reported to occur in the manufacture of large capacity DRAMs. To address both device requirements and yield limitations, new circuit technologies have been developed for 1 Gb DRAMs. By implementing a time-shared offset cancel sensing scheme and adopting a diagonal bit-line (DBL) cell, the chip size is reduced to 70% of that of a conventional DRAM. A defective word-line Hi-Z standby scheme and a flexible multi-macro architecture produces about twice the yield as that resulting from conventional architecture. 32 b I/Os with a pipeline circuit technique realizes a 400 MB/s data transfer rate. A 1 Gb DRAM with these features uses 0.25 /spl mu/m CMOS.

A 4-level storage 4 Gb DRAM

Bit-cost reduction is one of the most serious issues for file application DRAMs. Chip size reduction or density increase has been an effective solution. Lithographic technology has permitted this density increase through 70% reduction in the minimum design rule for each subsequent DRAM generation. However, for further density increase, another memory cell reduction technology is needed. Multi-level storage is one circuit technology that can reduce the effective cell size since it allows the storage of multiple voltage levels in a single memory cell functioning as a multi-bit memory. When four levels are stored in a single memory cell, the effective cell size is halved. The authors show that a charge-coupling sense amplifier, charge-sharing restore, and time-shared sensing increase speed and reduce sense-circuit area for 4 Gb DRAM.

A 7.68 GIPS 3.84 GB/s 1W parallel image processing RAM integrating a 16 Mb DRAM and 128 processors

A parallel image processing RAM (PIP-RAM) integrates a 16 Mb DRAM and 128 processor elements (PEs) on a single chip in 64 Mb DRAM process technology. There are three general design requirements when integrating DRAMs and processors onto a single chip: high-data-rate random access, low-power dissipation, and efficiently synchronized DRAM and processor. The PIP-RAM employs three circuit techniques in response to these requirements: (1) a paged-segmentation accessing (PSA), (2) a clocked low-voltage-swing differential-charge-transfer (CLD), and (3) a multiphase synchronization DRAM control (MSD) that uses a multiple-stage PLL. Large memory capacity and high-data-rate random access achieved by these techniques make the PIP-RAM suitable for image processing of large-scale, full-color pictures.

A 55-ns 16-Mb DRAM with built-in self-test function using microprogram ROM

A single 5-V power supply 16-Mb dynamic random-access memory (DRAM) has been developed using high-speed latched sensing and a built-in self-test (BIST) function with a microprogrammed ROM, in which automatic test pattern generation procedures were stored by microcoded programs. The chip was designed using a double-level Al wiring, 0.55- mu m CMOS technology. As a result, a 16-Mb CMOS DRAM with 55-ns typical access time and 130-mm/sup 2/ chip area was attained by implementing 4.05- mu m/sup 2/ storage cells. The installed ROM was composed of 18 words*10 b, where the marching test and checkerboard scan write/read test procedures were stored, resulting in successful self-test operation. As the BIST circuit occupies 1 mm/sup 2/ and the area overhead is about 1%, it proves to be promising for large-scale DRAMs. >

A boosted dual world-line decoding scheme for 256 Mb DRAMs

A boosted dual word-line decoding scheme with regulated power supply is developed to realize a memory cell applicable to 256 Mb DRAMs by using silicon dioxide as a dielectric material, and without area increase of the memory cell array. The scheme relaxes the wiring pitch on the cell array, thus making it easier to realize wiring patterns in the large step environment caused by the stack capacitor thickness. A capacitance of up to 50 fF can be realized for a dual cylindrical structure with 1 mu m height and 5 mm oxid thickness. The scheme yields word rising operations two times faster than conventional approaches.<<ETX>>

A 55 ns 16 Mb DRAM

The authors describe a 16-Mb CMOS DRAM (dynamic RAM) with 55-ns access time and 130-mm/sup 2/ chip area. It features a high-speed latched sensing (LS) scheme and a built-in self-test (BIST) function with a microprogrammable ROM in which automatic test pattern generation procedures are stored by microcoded programs. To achieve 55-ns access time, the DRAM combines the LS scheme with conventional double-Al-layer wiring and 5-V peripheral circuits. The bit-line sense circuits, driven at 3.3 V from an internal voltage converter to ensure 0.6 mu m MOS memory cell reliability, are shown. Both sensing speed and signal voltage are lower at 3.3 V operation than at 5 V operation. However, the LS scheme compensates for these drawbacks and achieves fast access time and high sensitivity. Operational waveforms for 55-ns row-address-strobe access time for a typical chip under normal conditions are shown, and chip characteristics are summarized.<<ETX>>

Electrical gate length measurement test structure for short channel MOSFET characteristics evaluation

The electrical characteristics and gate lengths of individual MOSFETs are evaluated by a test structure with a Kelvin pattern as the gate electrode. The gate length measurement by SEM can be substituted by the electrical measurement using this test structure. Excellent correspondence is obtained between the threshold voltage lowering in the short channel region and the electrically measured gate length. Furthermore, the precision of drain-to-gate overlap length is improved by applying the effective channel length extraction method to the electrically measured gate length instead of the commonly used designed gate length.

Separation of intrinsic and parasitic MOSFET parameters using a multiple built-in Kelvin test structure

A new MOSFET test structure built in multiple Kelvin patterns is used to evaluate scaled-down MOSFET characteristics through separation of intrinsic and parasitic parameters. Transistor characteristics and contact resistance of individual MOSFETs are simultaneously measured to clarify the direct correlation between fluctuation of MOSFET characteristics and that of parasitic contact resistance. MOSFET performance without parasitic interconnect resistance can be also measured to define intrinsic current drivability in a MOSFET fully scaled-down to less than sub-half-micrometers dimensions.