Isao Naritake

A 30-ns 256-Mb DRAM with a multidivided array structure

A 256-Mb DRAM with a multidivided array structure has been developed and fabricated with 0.25- mu m CMOS technology. It features 30-ns access time, 16-b I/Os, and a 35-mA operating current at a 60-ns cycle time. Three key circuit technologies were used in its design: a partial cell array activation scheme for reducing power-line voltage bounce and operating current, a selective pull-up data-line architecture to increase I/O width and reduce power dissipation, and a time-sharing refresh scheme to maintain the conventional refresh period without reducing operational margin. Memory cell size was 0.72 mu m/sup 2/. Use of the trench isolated cell transistor and the HSG cylindrical stacked capacitor cells helped reduce chip size to 333 mm/sup 2/. >

A 1-Gb DRAM for file applications

A number of large capacity DRAMs have been developed recently for file applications because data storage devices play an important role in high-speed communication and graphic systems. Such file memories must have low power dissipation, high data transfer rate and low cost. A low chip-yield problem is reported to occur in the manufacture of large capacity DRAMs. To address both device requirements and yield limitations, new circuit technologies have been developed for 1 Gb DRAMs. By implementing a time-shared offset cancel sensing scheme and adopting a diagonal bit-line (DBL) cell, the chip size is reduced to 70% of that of a conventional DRAM. A defective word-line Hi-Z standby scheme and a flexible multi-macro architecture produces about twice the yield as that resulting from conventional architecture. 32 b I/Os with a pipeline circuit technique realizes a 400 MB/s data transfer rate. A 1 Gb DRAM with these features uses 0.25 /spl mu/m CMOS.

A 4-level storage 4 Gb DRAM

Bit-cost reduction is one of the most serious issues for file application DRAMs. Chip size reduction or density increase has been an effective solution. Lithographic technology has permitted this density increase through 70% reduction in the minimum design rule for each subsequent DRAM generation. However, for further density increase, another memory cell reduction technology is needed. Multi-level storage is one circuit technology that can reduce the effective cell size since it allows the storage of multiple voltage levels in a single memory cell functioning as a multi-bit memory. When four levels are stored in a single memory cell, the effective cell size is halved. The authors show that a charge-coupling sense amplifier, charge-sharing restore, and time-shared sensing increase speed and reduce sense-circuit area for 4 Gb DRAM.

A 12-ns 8-Mbyte DRAM secondary cache for a 64-bit microprocessor

This paper describes three circuit technologies that have been developed for high-speed large-bandwidth on-chip DRAM secondary caches. They include a redundancy-array advanced activation scheme, a bus-assignment-exchangeable selector scheme and an address-zero access refresh scheme. By using these circuit technologies and new small subarray structures, a row-address access time of 12 ns and a row-address cycle time of 16 ns were obtained. An experimental chip made up of an 8-Mbyte DRAM and a 64-bit microprocessor was developed using 0.25-/spl mu/m merged logic and DRAM process technology.

A crossing charge recycle refresh scheme with a separated driver sense-amplifier for Gb DRAMs

A crossing charge recycle refresh (CCRR) scheme is proposed for large capacity DRAMs with hierarchical bit-line architecture, which reduces main bit-line charging current to 25% of that of conventional DRAMs. A separated driver sense-amplifier (SDSA) circuit is essential to realize this scheme because it features 11 times shorter charge transfer period than that of conventional sense amplifiers. These circuits are applied to an experimental 1-Gb DRAM.