Manabu Kojima

Advanced Metal Oxide Semiconductor and Bipolar Devices on Bonded Silicon‐on‐Insulators

Silicon-on-insulator devices have problems with both performance and cost. We developed three advanced devices on bonded SOI produced using pulse-field-assisted bonding and selective polishing in an attempt to solve these problems. We tightly bonded highly implanted wafers, epitaxial wafers, and wafers covered with smoothed CVD oxide at temperatures below 1000 o C. We uniformly thinned bonded wafers by grinding, polishing, resistivity-sensitive etching, or selective polishing. We formed buried layers and buried electrodes by bonding and polishing techniques. Our high speed epitaxial-base transistor on 1-μm thick SOI has a cutoff frequency of 32 GHz

Performance Boost using a New Device Design Methodology Based on Characteristic Current for Low-Power CMOS

The authors proposes a characteristic current (I_chr) to replace the conventional saturation drive current used to estimate approximate CMOS inverter delay times for deeply scaled devices. The authors also present a new device design method based on I_chr to achieve a higher operation frequency for CMOS inverter circuits. The new method shortens propagation delay time (Tpd) by 15%

A New SOI-Lateral Bipolar Transistor for High-Speed Operation

We proposed a new SOI-lateral bipolar transistor. The device is featured by a thin base (simulated thickness was 80 nm) and base contact which was formed just on an intrinsic base. The device has sufficient junction breakdown voltage, but a current gain of 10, due to the degraded forward-biased emitter-base junction characteristic. The current gain was improved to 30 by keeping the base region about 2 µm from the highly arsenic-implanted emitter. The device structure seems to be ideal for a future high-speed bipolar transistor.

High-speed epitaxial base transistors on bonded SOI

The authors propose fully isolated high-speed bipolar transistors using a photoepitaxial base and wafer-bonded SOI (silicon-on-insulator). A 0.7- mu m-thick buried layer that was highly doped by ion implantation before bonding was formed. Epitaxial base transistors (EBTs) on 1- mu m-thick bonded SOI were fabricated. The devices had a cutoff frequency of 32 GHz.<<ETX>>

Dual Conduction Characteristics Observed in Highly Resistive NbN Granular Thin Films

We observed in highly resistive NbN thin films at low temperature dual conduction characteristics in clearly separated two region of their sheet resistance. In the specimens with R Rc, however, the conduction characteristics can be explained supposing the KT effect for charge-soliton pairs.

Suppression of SiN-induced boron penetration by using SiH-free silicon nitride films formed by tetrachlorosilane and ammonia

Applications of SiH-free silicon nitride (SiN) films, formed by tetrachlorosilane (TCS) and ammonia, have been proved to effectively suppress the SiN-induced boron penetration. The SiN-induced boron penetration has been investigated in detail by using boron-doped polysilicon gated capacitors with several kinds of thick SiN films. It was clarified for the first time that the SiN-induced boron penetration becomes worse with SiH content in SiN films and deposition technique of SiH-free TCS-SiN films is essential for realization of the high-performance PMOSFETs.

Extension Engineering using Carbon co-Implantation Technology for Low Power CMOS Design with Phosphorus- and Boron-Extension

We have developed a carbon (C) co-implantation technology that enables drastic improvement of Vth rolloff in nMOSFET having phosphorus (P) extension while maintaining the current drive, and reduces the extension sheet resistance in pMOSFET having boron (B) extension. The data revealed that C introduced into the extension region suppresses the P-extension tail for nMOSFET and improves B activation ratio for pMOSFET. We also found that combination of C and indium (In) pocket plays an important role for Vth rolloff improvement in nMOSFET.

Lateral extension engineering using nitrogen implantation (N-tub) for high-performance 40-nm pMOSFETs

Lateral extension engineering using a nitrogen-implantation (N-tub) process has enabled high performance 40-nm pMOSFETs that overcome the trade-off between drive current and short channel immunity. The data show that an N dose of above 1/spl times/10/sup 14/ cm/sup -2/ effectively suppresses B diffusion, especially in the lateral extension tail. As a result, we realized a 13% improvement in CV/I from conventional process.

Advanced Input/Output Technology Using Laterally Modulated Channel Metal–Oxide–Semiconductor Field Effect Transistor for 65-nm Node System on a Chip

Advanced input/output (I/O) technology is reported for leading-edge system on a chip (SoC) applications, including high-speed I/O and RF circuits. Our device having a laterally modulated channel shows sufficient reliability even at 3.3 V operation with the same size as a conventional 2.5 V device. Since this technology also improves current drivability, the layout area of an I/O circuit block can be reduced down to 55% because of a reduced total gate width. Moreover, a metal-on-gate (MOG) option has been developed for RF applications, and an fmax of 55 GHz was achieved.

Quantized Current-Step Structure Observed in RF-Irradiated Microbridge Made of NbN Granular Thin Film

Qunatized current-step structure are observed in rf-irradiated Dayem type microbridges with narrow width made of very high resistance NbN granular thin film. The step width is found to be proportional to the irradiation frequency. Some discussion is made on the assumption that the structure is caused by a new macroscopic quantum effect dual to Shapiro step.