Volker Weinrich

Review of SrBi2Ta2O9 thin films capacitor processing

Abstract Ferroelectric memories (FeRAMs) are new types of memories especially suitable for mobile applications due to their unique properties like non-volatility, small DRAM-like cell size, fast read and write as well as low voltage/low power behavior. Although standard CMOS processes can be used for frontend and backend processes, FeRAM technology development has to overcome major challenges due to new materials used for capacitor formation. This work gives an overview of SrBi2Ta2O9 (SBT) thin films capacitor processing using Pt as electrode material. The study describes in detail SBT formation using metal organic deposition (MOD) as well as influence of electrode thickness and capacitor patterning on SBT electrical properties. Also, results for integration of the capacitor process into a 0.5μm CMOS process with 2-layer tungsten/aluminum metallization as well as stacked capacitor results are given.

A novel low-temperature (Ba,Sr)TiO 3 (BST) process with Ti/TiN barrier for Gbit DRAM applications

Abstract A new, low temperature (Ba,Sr)TiO 3 (BST) MOCVD process has been established at 580°C deposition temperature which can be used for Gbit DRAM applications using Ti TiN as barrier material. The process window for BST deposition was investigated in terms of deposition temperature, stoichiometry, film thickness, post annealing treatment and variation of the underlying electrode/barrier layer. Electrical characterization revealed specific capacitance values of 45 fF/μm 2 for 25 –30 nm film thickness and 75 fF/μm 2 for 10 nm film thickness which is close to the target value for GBit of 80 – 100 fF/μm 2 . Oxidation resistance of the Ti TiN barrier could be shown up to 600°C. Feasibility of this low temperature BST process has been successfully demonstrated using a 4 Mbit test vehicle.

Influence of dry etching using argon on structural and electrical properties of crystalline and non-crystalline SrBi2Ta2O9 thin films

Abstract After patterning the Platinum/crystalline SrBi2Ta2O9 bilayer by Argon based Reactive Ion Etching (RIE), a degradation of the remanent polarization and leakage current of the capacitors for smaller feature sizes is observed. To simulate the study of the side wall of the capacitors, etching of blanket SBT is used as a model experiment. It is shown that etching of crystalline SBT is damaging the SBT material, resulting in the formation of small crystallites (SEM), the appearance of an unknown peak (XRD) and reduction of the Bismuth content on the SBT surface (AES). Using non-crystalline SBT, neither a degradation of electrical properties for smaller feature sizes nor a structural damage of blanket SBT is found after etching and recrystallization annealing although after etching of non-crystalline SBT also a loss of Bi is seen as indicated by AES. Therefore the following model is proposed: Patterning the Pt/crystalline SBT capacitor leads to a Bi deficient edge of the dielectric. Due to the crystalli...

Role of recovery anneals for chemical solution deposition (CSD) based SrBi2Ta2O9 (SBT) thin films

Abstract Using a recovery anneal after deposition of the Pt top electrode and patterning the Platinum / SrBi2Ta2O9 bilayer has been established to obtain well shaped hysteresis curves with low leakage currents. Electrical properties of SBT test capacitors in dependence of temperature and time for the recovery anneal are discussed. Evidence for degradation of the electrical properties of SBT capacitors after patterning due to the appearance of a new unknown peak in X-ray diffraction (XRD) is presented.

Production worthy method to structure platinum electrodes for ferroelectric devices elisabeth

Abstract Platinum (Pt) is a viable electrode material for use with ferroelectric films to form FeRAM cells. Due to the chemical stability of Pt etching at low-temperature, drawbacks like tapered Pt profiles with poor CD control and low mean time between cleans are resulting. In this work plasma etching of sub-micron Pt electrodes with vertical and veil-free profiles was successfully demonstrated. This was obtained by maintaining substrate temperatures >250°C, assisting etch by-product volatility and promotion of necessary chemical reactions. The production worthiness of high-temperature Pt etching was evaluated by a marathon run on simulated product material while monitoring the process parameter stability. Production was successfully simulated by 950 product like substrates for more than 34 plasma hours. Stable wafer-to-wafer performance in all monitored parameters demonstrated the production worthiness of this platinum electrode structuring method for applications in FeRAM manufacturing.