Mantu K. Hudait

High-performance 40nm gate length InSb p-channel compressively strained quantum well field effect transistors for low-power (VCC=0.5V) logic applications

This paper describes for the first time, a high-speed and low-power III-V p-channel QWFET using a compressively strained InSb QW structure. The InSb p-channel QW device structure, grown using solid source MBE, demonstrates a high hole mobility of 1,230 cm2/V-s. The shortest 40 nm gate length (LG) transistors achieve peak transconductance (Gm) of 510 muS/mum and cut-off frequency (fT) of 140 GHz at supply voltage of 0.5V. These represent the highest Gm and fT ever reported for III-V p-channel FETs. In addition, effective hole velocity of this device has been measured and compared to that of the standard strained Si p-channel MOSFET.

Advanced high-K gate dielectric for high-performance short-channel In 0.7 Ga 0.3 As quantum well field effect transistors on silicon substrate for low power logic applications

This paper describes integration of an advanced composite high-K gate stack (4nm TaSiO<inf>x</inf>-2nm InP) in the In<inf>0.7</inf>Ga<inf>0.3</inf>As quantum-well field effect transistor (QWFET) on silicon substrate. The composite high-K gate stack enables both (i) thin electrical oxide thickness (t<inf>OXE</inf>) and low gate leakage (J<inf>G</inf>) and (ii) effective carrier confinement and high effective carrier velocity (V<inf>eff</inf>) in the QW channel. The L<inf>G</inf>=75nm In<inf>0.7</inf>Ga<inf>0.3</inf>As QWFET on Si with this composite high-K gate stack achieves high transconductance of 1750µS/µm and high drive current of 0.49mA/µm at V<inf>DS</inf>=0.5V.

Electrical transport characteristics of Au/n-GaAs Schottky diodes on n-Ge at low temperatures

The currenti?½voltage characteristics of Au/n-GaAs Schottky diodes grown by metal-organic vapor-phase epitaxy on Ge substrates were determined in the temperature range 80i?½300 K. The zero-bias barrier height for current transport decreases and the ideality factor increases at low temperatures. The ideality factor was found to show the T0 effect and a higher characteristic energy. The excellent matching between the homogeneous barrier height and the effective barrier height was observed and infer good quality of the GaAs film. No generationi?½recombination current due to deep levels arising during the GaAs/Ge heteroepitaxy was observed in this study. The value of the Richardson constant was found to be 7.04 A K?2 cm?2, which is close to the value used for the determination of the zero-bias barrier height.

Effects of thin oxide in metal–semiconductor and metal–insulator–semiconductor epi-GaAs Schottky diodes

The current–voltage (I–V) and capacitance–voltage (C–V) characteristics of metal–insulator–semiconductor (MIS) GaAs Schottky diodes are investigated and compared with metal–semiconductor (MS) diodes. The MIS diode showed nonideal behavior of I–V characteristics with an ideality factor of 1.17 and a barrier height of 0.97 eV. The energy distribution of interface states density was determined from the forward bias I–V characteristics by taking into account the bias dependence of the effective barrier height, though it is small. The reduction in the saturation current in the MIS case is caused by a thin oxide layer and is due to the combination of increased barrier height and a decrease in the Richardson constant. The carrier concentration anomaly observed between the MIS and MS diodes measured from reverse bias C–V measurements is explained via oxide

Ultrahigh-Speed 0.5 V Supply Voltage

(\beta-Ga_2O_3)

\hbox{In}_{0.7} \hbox{Ga}_{0.3}\hbox{As}

traps due to the Ga-vacancy by deep level transient spectroscopy (DLTS) measurement.

Quantum-Well Transistors on Silicon Substrate

The direct epitaxial growth of ultrahigh-mobility InGaAs/InAlAs quantum-well (QW) device layers onto silicon substrates using metamorphic buffer layers is demonstrated for the first time. In this letter, 80 nm physical gate length depletion-mode InGaAs QW transistors with saturated transconductance gm of 930 muS / mum and fT of 260 GHz at VDS = 0.5 V are achieved on 3.2 mum thick buffers. We expect that compound semiconductor-based advanced QW transistors could become available in the future as very high-speed and ultralow-power device technology for heterogeneous integration with the mainstream silicon CMOS.

The influences of surface treatment and gas annealing conditions on the inversion behaviors of the atomic-layer-deposition Al2O3/n-In0.53Ga0.47As metal-oxide-semiconductor capacitor

The inversion behaviors of atomic-layer-deposition Al2O3/n-In0.53Ga0.47As metal-oxide-semiconductor capacitors are studied by various surface treatments and postdeposition annealing using different gases. By using the combination of wet sulfide and dry trimethyl aluminum surface treatment along with pure hydrogen annealing, a strong inversion capacitance-voltage (C-V) response is observed, indicating a remarkable reduction in interface trap state density (Dit) at lower half-part of In0.53Ga0.47As band gap. This low Dit was confirmed by the temperature independent C-V stretch-out and horizontal C-V curves. The x-ray photoelectron spectroscopy spectra further confirm the effectiveness of hydrogen annealing on the reduction of native oxides.

Fermi level unpinning of GaSb (100) using plasma enhanced atomic layer deposition of Al2O3

N-type and p-type GaSb metal-oxide-semiconductor capacitors (MOSCAPs) with atomic-layer-deposited (ALD) and plasma-enhanced-ALD (PEALD) Al2O3 dielectrics are studied to identify the optimum surface preparation and oxide deposition conditions for a high quality oxide-semiconductor interface. The ALD Al2O3/GaSb MOSCAPs exhibit strongly pinned C-V characteristics with high interface state density (Dit) whereas the PEALD Al2O3/GaSb MOSCAPs show unpinned C-V characteristics (low Dit). The reduction in Sb2O3 to metallic Sb is suppressed for the PEALD samples due to lower process temperature, identified by x-ray photoelectron spectroscopy analysis. Absence of elemental Sb is attributed to unpinning of Fermi level at the PEALD Al2O3/GaSb interface.N-type and p-type GaSb metal-oxide-semiconductor capacitors (MOSCAPs) with atomic-layer-deposited (ALD) and plasma-enhanced-ALD (PEALD) Al2O3 dielectrics are studied to identify the optimum surface preparation and oxide deposition conditions for a high quality oxide-semiconductor interface. The ALD Al2O3/GaSb MOSCAPs exhibit strongly pinned C-V characteristics with high interface state density (Dit) whereas the PEALD Al2O3/GaSb MOSCAPs show unpinned C-V characteristics (low Dit). The reduction in Sb2O3 to metallic Sb is suppressed for the PEALD samples due to lower process temperature, identified by x-ray photoelectron spectroscopy analysis. Absence of elemental Sb is attributed to unpinning of Fermi level at the PEALD Al2O3/GaSb interface.

Interface states density distribution in Au/n-GaAs Schottky diodes on n-Ge and n-GaAs substrates

The current–voltage (I–V) and capacitance–voltage (C –V) characteristics of Au/n-GaAs Schottky diodes on n-Ge substrates are investigated and compared with characteristics of diodes on GaAs substrates. The diodes show the non-ideal behavior of I– V characteristics with an ideality factor of 1.13 and barrier height of 0.735 eV. The forward bias saturation current was found to be large (3 ×10 −10 A vs. 4.32 ×10 − 12 A) in the GaAs/Ge Schottky diodes compared with the GaAs/GaAs diodes. The energy distribution of interface states was determined from the forward bias I–V characteristics by taking into account the bias dependence of the effective barrier height, though it is small. The interface states density was found to be large in the Au/n-GaAs/n-Ge structure compared with the Au/n-GaAs/n + -GaAs structure. The possible explanation for the increase in the interface states density in the former structure was highlighted.