Ravi Pillarisetty

Academic and industry research progress in germanium nanodevices

Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.

Fabrication, characterization, and physics of III–V heterojunction tunneling Field Effect Transistors (H-TFET) for steep sub-threshold swing

This work demonstrates the steepest subthreshold swing (SS < 60mV/decade) ever reported in a III–V Tunneling Field Effect Transistor (TFET) by using thin gate oxide, heterojunction engineering and high source doping. Owing to a lower source-to-channel tunnel barrier height, heterojunction III–V TFETs demonstrate steeper subthreshold swing (SS) at a given drain current (ID) and improved drive current compared to the homojunction III–V TFETs. Electrical oxide thickness (EOT) scaling and increased source doping in tandem with tunnel barrier height reduction are shown to greatly improve the SS of the III–V TFETs and increase ID by more than 20X.

High-performance 40nm gate length InSb p-channel compressively strained quantum well field effect transistors for low-power (VCC=0.5V) logic applications

This paper describes for the first time, a high-speed and low-power III-V p-channel QWFET using a compressively strained InSb QW structure. The InSb p-channel QW device structure, grown using solid source MBE, demonstrates a high hole mobility of 1,230 cm2/V-s. The shortest 40 nm gate length (LG) transistors achieve peak transconductance (Gm) of 510 muS/mum and cut-off frequency (fT) of 140 GHz at supply voltage of 0.5V. These represent the highest Gm and fT ever reported for III-V p-channel FETs. In addition, effective hole velocity of this device has been measured and compared to that of the standard strained Si p-channel MOSFET.

Electrostatics improvement in 3-D tri-gate over ultra-thin body planar InGaAs quantum well field effect transistors with high-K gate dielectric and scaled gate-to-drain/gate-to-source separation

In this work, 3-D Tri-gate and ultra-thin body planar InGaAs quantum well field effect transistors (QWFETs) with high-K gate dielectric and scaled gate-to-source/gate-to-drain (LSIDE) have been fabricated and compared. For the first time, 3-D Tri-gate InGaAs devices demonstrate electrostatics improvement over the ultra-thin (QW thickness, TQW=10nm) body planar InGaAs device due to (i) narrow fin width (WFIN) of 30nm and (ii) high quality high-K gate dielectric interface on the InGaAs fin. Additionally, the 3-D Tri-gate InGaAs devices in this work achieve the best electrostatics, as evidenced by the steepest SS and the smallest DIBL, ever reported for any high-K III–V field effect transistor. The results in this work show that the 3-D Tri-gate device architecture is an effective way to improve the scalability of III–V FETs for future low power logic applications.

Non-planar, multi-gate InGaAs quantum well field effect transistors with high-K gate dielectric and ultra-scaled gate-to-drain/gate-to-source separation for low power logic applications

In this work, non-planar, multi-gate InGaAs quantum well field effect transistors (QWFETs) with high-K gate dielectric and ultra-scaled gate-to-drain and gate-to-source separations (LSIDE) of 5nm are reported for the first time. The high-K gate dielectric formed on this non-planar device structure has the expected thin TOXE of 20.5Å with low JG, and high quality gate dielectric interface. The simplified S/D scheme is needed for the non-planar architecture while achieving significant reduction in parasitic resistance. Compared to the planar high-K InGaAs QWFET with similar TOXE, the non-planar, multi-gate InGaAs QWFET shows significantly improved electrostatics due to better gate control. The results of this work show that non-planar, multi-gate device architecture is an effective way to improve the scalability of III–V QWFETs for low power logic applications.

Heterogeneous integration of enhancement mode in 0.7 ga 0.3 as quantum well transistor on silicon substrate using thin (les 2 μm) composite buffer architecture for high-speed and low-voltage ( 0.5 v) logic applications

This paper describes for the first time, the heterogeneous integration of In0.7Ga0.3As quantum well device structure on Si substrate through a novel, thin composite metamorphic buffer architecture with the total composite buffer thickness successfully scaled down to 1.mum, resulting in high- performance short-channel enhancement-mode In0.7Ga0.3As QWFETs on Si substrate for future high-speed digital logic applications at low supply voltage such as 0.5 V.

High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (Vcc = 0.5 V) III–V CMOS architecture

In this article we demonstrate a Ge p-channel QWFET with scaled TOXE = 14.5Å and mobility of 770 cm2/V*s at ns =5×1012 cm−2 (charge density in the state-of-the-art Si transistor channel at Vcc = 0.5V). For thin TOXE < 40 Å, this represents the highest hole mobility reported for any Ge device and is 4× higher than state-of-the-art strained silicon. The QWFET architecture achieves high mobility by incorporating biaxial strain and eliminating dopant impurity scattering. The thin TOXE was achieved using a Si cap and a low Dt transistor process, which has a low oxide interface Dit. Parallel conduction in the SiGe buffer was suppressed using a phosphorus junction layer, allowing healthy subthreshold slope in Ge QWFET for the first time. The Ge QWFET achieves an intrinsic Gmsat which is 2× higher than the InSb p-channel QWFET [3]. These results suggest the Ge QWFET is a viable p-channel option for non-silicon CMOS.

Logic performance evaluation and transport physics of Schottky-gate III–V compound semiconductor quantum well field effect transistors for power supply voltages (V CC ) ranging from 0.5v to 1.0v

In this paper for the first time, the logic performance of Schottky-gate In<inf>0.7</inf>Ga<inf>0.3</inf>As QWFETs is measured and evaluated against that of advanced Strained Si MOSFETs from Vcc = 0.5 to 1.0V. The QWFET is shown to have measured drive current gain over the Si MOSFET for the entire Vcc range. Effective velocity (V<inf>eff</inf>) of the QWFET exhibits 4.6X–3.3X gain over the Si MOSFET. The high V<inf>eff</inf> enables 65% intrinsic drive current gain at V<inf>CC</inf> = 0.5V and 20% gain at V<inf>CC</inf> = 1.0V for the In<inf>0.7</inf>Ga<inf>0.3</inf>As QWFET over that of Strained Si, despite 2.5x lower charge density.

Experimental observation and physics of “negative” capacitance and steeper than 40mV/decade subthreshold swing in Al 0.83 In 0.17 N/AlN/GaN MOS-HEMT on SiC substrate

GaN is a promising material for LED lighting [1], high voltage power electronics [2] and high power RF applications [3]. GaN HEMT and MOS-HEMT with AlGaN [4] or AlInN [5] polarization layer have been widely studied. In this work we investigate the effects of Al_0.83In_0.17N polarization layer thickness scaling on the device characteristics of Al_0.83In_0.17N/AlN/GaN MOS-HEMTs on SiC substrates. We have experimentally observed “negative” capacitance and subthreshold swing (SS) steeper than 40 mV/dec in GaN MOS-HEMTs with thin Al_0.83In_0.17N polarization layer, where composition modulation of Al% and In% is observed.

High mobility strained p-channel germanium quantum well field effect transistor for low power (Vcc = 0.5 V) III–V CMOS applications

In this talk, we review recent research results[1] investigating the germanium quantum well field effect transistor (QWFET) for use as the p-channel device option for future low power (Vcc = 0.5V) III–V CMOS architecture. We demonstrate a high mobility Ge p-channel QWFET, with scaled TOXE = 14.5Å and mobility of 770 cm²/V*s at n<inf>s</inf> =5×10¹² cm⁻². For TOXE &#60; 40 Å, this represents the highest hole mobility reported for any Ge device and is 4x higher than state-of-the-art strained silicon [2]. Furthermore, at Vcc = 0.5V, the Ge QWFET exhibits 2x higher drive current at fixed Ioff than the best III–V [3] and germanium devices [4] reported to date. These results suggest the Ge QWFET is a viable p-channel option for non-silicon CMOS.