Robert J. Wenzel

The Redistributed Chip Package: A Breakthrough for Advanced Packaging

The redistributed chip package (RCP) is a substrate-less embedded chip package that offers a low-cost, high performance, integrated alternative to current wirebond BGA and flip chip BGA packaging. Devices are encapsulated into panels while routing of signals, power, and ground is built directly on the panel. The RCP panel and signal build-up lowers the cost of the package by eliminating wafer bumping and substrates thereby enabling large scale assembly in panel form. The build-up provides better routing capabilities and better integration. Also, by eliminating bumping, the device interconnect is inherently Pb-free, and the stress of the package is reduced enabling ultra-low K device compatibility. The panel is created by attaching device active side down to a substrate, encapsulating and curing the devices, grinding to desired thickness, and then removing the substrate. Signal, power, and ground planes are created using redistribution-like processing. Multi-layer metal RCP packages have passed -40 to 125C air-to-air thermal cycling and HAST after MSL3/260 preconditioning.

Advanced Packaging: The Redistributed Chip Package

The redistributed chip package (RCP) is a substrate-less embedded chip package that offers a low-cost, high performance, integrated alternative to current wirebond ball grid array (BGA) and flip chip BGA packaging. Devices are encapsulated into panels while routing of signals, power, and ground is built directly on the panel. The RCP panel and signal build up lowers the cost of the package by eliminating wafer bumping and substrates thereby enabling large scale assembly in panel form. The build up provides better routing capabilities and better integration. Also, by eliminating bumping, the device interconnect is inherently Pb-free, and the stress of the package is reduced enabling ultra-low-k device compatibility. The panel is created by attaching the device active side down to a substrate, encapsulating and curing the devices, grinding to desired thickness, and then removing the substrate. Signal, power, and ground planes are created using redistribution-like processing. Multilayer metal RCP packages have passed 40 to 125 C air-to-air thermal cycling and HAST after MSL3/260 preconditioning.

Implementation of a mobile phone module with redistributed chip packaging

The redistributed chip packaging is an embedded chip technology that eliminates the need for wirebonds and flip chip bumps. This technology enables smaller packages at a lower cost, while providing improved mechanical, electrical and thermal performance. The process involves producing panels placing the chip active face down along with an embedded ground plane (EGP) and screen printing encapsulant to embed the die. Subsequently alternate layers of dielectric and Cu metallization are built up and the packages are sawn into individual units. The use of wafer fabrication tools enables finer lines and spaces in the build-up layers. This paper will discuss process conditions during the panelization and the integration of the base function of an i.275 GSM/EDGE mobile phone into a single module measuring a maximum of 1 square inch. The design of the EGP and the role of simulations to achieve a robust, reliable package will also be discussed. The outputs included moisture sensitivity level (MSL) 3 testing, air-to-air thermal cycling (- 40C/125C) and unbiased highly accelerated stress testing (HAST). Testing of RCP packages will also be discussed.

Inductance Extraction for Interconnects in the Presence of Nonlinear Magnetic Materials

The existence of nonlinear magnetic materials poses a challenge to the interconnect inductance extraction for circuits in micromotors, radio-frequency identification, and magnetoresistive random access memory. In this paper, we present a fast algorithm to extract inductance in the presence of nonlinear magnetic materials. The new algorithm models the nonlinear magnetic characteristics by solving the Landau-Lifshitz-Gilbert equation, and the nonhomogeneous magnetic characteristics by introducing a fictitious magnetic charge. To speed up the algorithm, we apply a number of innovative techniques, including the approximation of magnetic charge effect and the modeling of currents with solenoidal basis. Experimental results demonstrate the accuracy and efficiency of the new algorithm. Its relative error with respect to the commercial tool is below 3%, while its speed is up to one magnitude faster.

A study of split and common ground referencing schemes for a high speed bus

Two different module referencing schemes, one with split ground planes between transmit/receive (TX/RX), and the other with a common ground plane, are first compared using models generated from 3D full-wave solver, and then the two different module designs are built and tested. The measurements performed and test data on the manufactured modules includes TX output high-low amplitude, eye height, RX jitter tolerance, Phase-Lock-Loop (PLL) interference, and jitter transfer function testing for the transmitter. The data indicates that the common ground referencing scheme results in superior performance for the high speed interface.

Prediction of maximum operating frequency for packaged microprocessor using measurements and modeling

This paper introduces a method to predict of the impact of packaging changes on microprocessor maximum operating frequency (Fmax). This is useful both in package technology selection and subsequent design optimization. The method uses power draw versus frequency and Fmax versus supply voltage data to enable time-domain circuit simulations using a resistive-acting dissipative core model instantiated within a field-solver-based model of the package. Measurements and simulations are carried out for an existing part that is packaged in a first, characterization package, in order to back out a theoretical intrinsic Fmax versus supply voltage curve for the package-free device. Subsequent circuit simulations using alternative package models can then be used to find the new Fmax for the device in a new package of interest that may not yet be fabricated. The method is useful for tasks such as predicting the outcome of reduced cost re-packaging of existing parts or estimating package effect on new similar parts in a family of parts.