Marc A. Rossow

Dual Silicide SOI CMOS Integration with Low-Resistance PtSi PMOS Contacts

We demonstrate a dual silicide integration on a SOI CMOS platform with robust low-resistance PtSi PMOS contacts. Compared to NiSi, the specific contact resistivity is reduced in PtSi contacts to p-type Si and increased in contacts to n-type Si. PMOS linear and saturation drive current enhancements of 6% and 9%, respectively, were achieved with PtSi relative to baseline NiSi source/drain contacts.

Metrology Of Silicide Contacts For Future CMOS

Silicide materials (NiSi, CoSi2, TiSi2, etc) are used to form low‐resistance contacts between the back‐end (W plugs and Cu interconnects) and front‐end portions (silicon source, drain, and gate regions) of integrated CMOS circuits. At the 65 nm node, a transition from CoSi2 to NiSi was necessary because of the unique capability of NiSi to form narrow silicide nanowires on active (monocrystalline) and gate (polycrystalline) lines. Like its predecessors TiSi2 and CoSi2, NiSi is a mid‐gap silicide, i.e., the Fermi level of the NiSi metal is pinned half‐way between the conduction and valence band edges in silicon. This leads to a Schottky barrier between the silicide and silicon source‐drain regions, which creates undesirable parasitic resistances. For future CMOS generations, band‐edge silicides, such as PtSi for contacts to p‐type or rare earth silicides for contacts to n‐type Si will be needed. This paper reviews metrology and characterization techniques for NiSi process control for development and manufac...

Implementing an In Situ Surface Preparation Prior to Ni Deposition for Ni Salicide Processes

Self-aligned silicides (salicides) are used to fabricate low-resistance gate and source/drain contacts for advanced CMOS devices. At the sub-100nm technology and beyond, Ni replaces cobalt due to its lower reaction temperature, low line-width sensitivity, and lower Si consumption [1]. A critical step in the salicide module is the surface preparation prior to Ni deposition. A pre-deposition in-situ Ar sputter preclean has traditionally been used for this purpose with Co and Ti salicides. However, if not optimized, the process leaves undesired re-sputtered Si on the gate spacer. This causes leakage between the source/drain and gate electrodes [2,3]. Besides Ar sputter, other in-situ surface preparation methods have also been developed and reported by other investigators [4,5]. In this study, the effects of in-situ surface preparation processes prior to Ni deposition were investigated.