Marc Fouchier

Benefits of plasma treatments on critical dimension control and line width roughness transfer during gate patterning

The present work focuses on the line width roughness (LWR) transfer and the critical dimension control during a typical gate stack patterning and shows the benefits of introducing 193 nm photoresist treatments before pattern transfer into the gate stack to improve process performance. The two investigated treatments (HBr plasma and vacuum ultra violet (VUV) plasma radiation) have been tested on both blanket photoresist films and resist patterns to highlight the etching and roughening mechanisms of cured resists. Both treatments reinforce the etch resistance of the photoresist exposed to fluorocarbon plasma etching process used to open the Si-ARC (silicon antireflective coating) layer. The etch resistance improvement of cured resists is attributed to both the decrease in oxygen content within the resist and the crosslinking phenomena caused by VUV radiation during the treatment. As the magnitude of the surface roughness is directly correlated to the etched thickness, cured resists, which are etched less rapidly, will develop a lower surface roughness for the same processing time compared to reference resists. The LWR evolution along the pattern sidewalls has been studied by critical dimension atomic force microscopy during the Si-ARC plasma etching step. The study shows that the LWR is degraded at the top of the resist pattern and propagates along the pattern sidewalls. However, as long as the degradation does not reach the interface between resist and Si-ARC, the LWR decreases during the Si-ARC etching step. As resist pretreatments reinforce the resist etch resistance during Si-ARC etching, the LWR degradation along the sidewalls is limited leading to minimized LWR transfer. The LWR decrease observed after plasma etching has been explained thanks to a spectral analysis of the LWR performed by critical dimension scanning electron microscopy combined with the power spectral density fitting method. The study shows that the high and medium frequency components of the roughness (periodicity below 200 nm) are not totally transferred during the gate patterning allowing a LWR decrease at each plasma step.

Etching mechanisms of thin SiO2 exposed to Cl2 plasma

Plasma etching is the most standard patterning technology used in micro- and nano-technologies. Chlorine-based plasmas are often used for silicon etching. However, the behavior of thin silicon oxide exposed to such a plasma is still not fully understood. In this paper, we investigate how a thin silicon oxide layer on silicon behaves when it is exposed to a Cl2 plasma. The authors show that chlorine atoms diffuse and/or Cl+ ions are implanted through the thin (<2.5 nm) oxide, leading to the formation of a SiClx interface layer between the two layers of Si and SiO2. Chlorine accumulates at the interface until the SiO2 is thin enough to release volatile SiClx species and the silicon begins to be etched.

Plasma treatments to improve line-width roughness during gate patterning

Abstract. The major issue related to line width roughness (LWR) is the significant LWR of the photoresist patterns printed by 193-nm lithography that is partially transferred into the gate stack during the subsequent plasma etching steps. The strategy used today to overcome this issue is to apply postlithography treatments to reduce photoresist pattern LWR before transfer. In this article, we investigate the impact of various plasma treatments (HBr, H2, He, Ar) on the minimization of the LWR of dense and isolated photoresist patterns and its transfer during gate patterning. To do so, we use critical dimension scanning electron microscopy measurements combined with power spectrum density fitting method to extract unbiased LWR values and provide a spectral analysis of the LWR. We show that plasma treatments that lead to carbon redeposition from the gas phase on the resist pattern sidewalls are less efficient to reduce LWR than plasma treatments where the redeposition is limited. Among all plasma chemistries, H2 plasmas seem very promising to decrease resist LWR in the whole spectral range, while maintaining square resist profiles. In addition, we show that all frequency roughness components are not equally transferred during gate patterning, and more particularly that the high frequency roughness components are lost.

Atomic-scale silicon etching control using pulsed Cl2 plasma

Plasma etching has been a key driver of miniaturization technologies toward smaller and more powerful devices in the semiconductor industry. Thin layers involved in complex stacks of materials are approaching the atomic level. Furthermore, new categories of devices have complex architectures, leading to new challenges in terms of plasma etching. New plasma processes that are capable to etch ultra-thin layers of materials with control at the atomic level are now required. In this paper, the authors demonstrate that Si etching in Cl2 plasma using plasma pulsing is a promising way to decrease the plasma-induced damage of materials. A controlled etch rate of 0.2 nm min−1 is reported by pulsing the chlorine plasma at very low duty cycles. Using quasi-in-situ angle resolved XPS analyses, they show that the surface of crystalline silicon is less chlorinated, the amorphization of the top crystalline silicon surface is decreased, and the chamber wall are less sputtered in pulsed plasmas compared to continuous wave plasmas. This is attributed to the lower density of radicals, lower ion flux, and lower V-UV flux when the plasma is pulsed.

Vacuum UV broad-band absorption spectroscopy: a powerful diagnostic tool for reactive plasma monitoring

Broad band UV?visible absorption spectroscopy is widely used to measure the concentration of radicals in reactive plasmas. We extended the applicability of this technique to the VUV (115?nm to 200?nm), the spectral range in which the electronic transitions from the ground state to the Rydberg or pre-dissociated states of many closed-shell molecules are located. This gives access to the absolute densities of species which do not, or weakly absorb in the UV?visible range. The technique is demonstrated by measuring the densities of HBr and Br2 molecules in HBr high-density ICP plasmas.

Smoothing mechanisms involved in thermal treatment for linewidth roughness reduction of 193-nm photoresist patterns

Strategies to reduce gate linewidth roughness (LWR) down to the 2 nm required for the sub-20 nm technological node have fallen short. The typical approach is still to apply postlithography treatments to reduce photoresist pattern LWR before transfer. Thermal processing is one among the considered resist smoothing techniques that proved to reduce LWR efficiently. In this study, the authors investigate the smoothing mechanisms involved and show that LWR reduction is linked to the outgassing of deprotected leaving groups present at edge surfaces of the photoresist pattern. Thermal treatment is not as efficient as plasma treatment to reduce 193-nm photoresist linewidth roughness, but results from study suggest that the combination of thermal and plasma treatments could lead to further improvements in LWR.

Plasma treatment to improve linewidth roughness during gate patterning

With the decrease of semiconductor device dimensions, line width roughness (LWR) becomes a challenging parameter that needs to be controlled below 2nm in order to ensure good electrical performances of CMOS devices of the future technological nodes. One issue is the significant LWR of the photoresist patterns printed by 193nm lithography that is known to be partially transferred into the gate stack during the subsequent plasma etching steps. This issue could be partially resolved by applying plasma pre treatment on photoresist before plasma transfer. Another issue is linked to the noise level of the metrology tool, that causes a non negligible bias from true LWR values. Recently we proposed an experimental protocol combining CD-SEM measurements and Power Spectral Density (PSD) fitting method for an accurate estimation of the CDSEM noise level and extraction of unbiased LWR. In this article, we use the developed CDSEM protocol to extract roughness parameters (true LWR, correlation length, fractal exponent) of dense and isolated photoresist patterns exposed to various plasma treatments (HBr, H2, He, Ar), and also to follow the evolution of the LWR during the subsequent plasma etching steps involved in gate patterning. We show that the resist LWR is less improved in isolated than in dense lines with HBr plasma treatment because of carbon species redeposition more important on isolated resist pattern sidewalls. Plasmas such as H2 that limit carbon redeposition are more efficient to decrease significantly resist LWR in both dense and isolated lines. In addition we show that all frequency roughness components are not equally transferred during gate patterning, and more particularly that the high frequency roughness components are lost.

Gate patterning strategies to reduce the gate shifting phenomenon for 14 nm fully depleted silicon-on-insulator technology

The complexification of integrated circuit designs along with downscaling introduces new patterning challenges. In logic process integration, it is found that the gate etch process flow introduces a few nanometer displacement of the gate patterns from their original position fixed by the lithography layout. This phenomenon referred to gate shifting (GS) generates a contact to gate overlay misplacement that compromises the transistor electrical performance. HBr cure plasma, which is a well-established postlithography treatment to increase photoresist stability and improves both line edge roughness (LER) and critical dimension uniformity during pattern transfer, has been identified as the root cause of the gate shifting phenomenon. The vacuum ultraviolet (VUV) irradiation emitted by HBr plasma leads to an asymmetric flowing of the two-dimensional resist patterns, and thus to a displacement of the gate patterns. Based on plasma optical emission measurements, the HBr plasma conditions are optimized to limit t...

Spectral analysis of sidewall roughness during resist-core self-aligned double patterning integration

Double patterning technology has now proved its efficiency to go beyond the standard lithographic printing limits and address the resolution requirements of the sub-20 nm technological node. However, some data are still lacking regarding the characterization of line edge/width roughness (LER/LWR) in such integration. In this work, a detailed spectral analysis of the sidewall roughness evolution during a resist-core self-aligned double patterning (SADP) integration is presented. A 20 nm half-pitch SADP process using photoresist as the core material, and SiO2 deposited by plasma enhanced atomic layer deposition as the spacer material is developed. The LER and LWR have been characterized at each technological step involved in the SADP process flow, using a power spectral density fitting method, which provides a full description of the sidewalls roughness with the estimation of noise-free roughness amplitude (σ), correlation length (ξ), and roughness exponent (α). Results show that the SADP process allows to ...

Atomic force microscopy study of photoresist sidewall smoothing and line edge roughness transfer during gate patterning

Abstract. With the constant decrease of semiconductor device dimensions, gate line edge roughness (LER) becomes an important source of device variability. Gate LER originates from photoresist (PR) LER that is partially transferred into the gate during plasma etching. A plasma treatment is typically used to reduce the PR LER before the transfer. LER control at the nanometer scale also requires accurate measurements. We have recently developed a technique for LER measurement based upon atomic force microscopy (AFM). In this technique, the sample is tilted at about 45 deg and feature sidewalls are scanned along their length with the AFM tip to obtain three-dimensional images. The AFM technique is applied to the study of a pattern transfer into a gate stack starting from untreated PR, PR treated by conventional HBr plasma, and PR treated by HBr/O2 plasma followed by a bake at 150°C. It is found that the plasma etching reduces the LER at each etching step. The reduction is more important when starting from untreated PR which has the highest initial LER. However, the final LER in the Si layer remains significantly smaller when starting with cured PR, especially with PR cured by an HBr/O2 plasma treatment followed by a bake at 150°C.