Marc Strasser

Miniaturized Thermoelectric Generators Based on Poly-Si and Poly-SiGe Surface Micromachining

We report on miniaturized thermoelectric generators which are being developed to convert waste heat into a few µW of electrical power sufficient to supply microelectronic circuitry. A BiCMOS realization using standard materials is favored to make these generators amenable to low cost applications. In order to optimize our device, the design and the material properties have been studied. The use of micromachining techniques allowed us to improve the thermal efficiency of the generator significantly. Low thermal conductivity of the thermoelectric materials proved to be the most important factor to increase the output power. The materials we have investigated are poly-Si and poly-SiGe. Experimental results of the fabricated devices show good agreement with the predictions of thermal simulations.

Automotive 130 nm smart-power-technology including embedded flash functionality

In this paper a 130 nm BCD technology platform is presented. The process offers logic-devices, flash-devices and high voltage devices with rated voltages up to 60 V. There are HV analog devices with variable channel length and HV power devices with low on-resistances. To ensure the safe operation of the power devices, a superior robustness against high energetic pulses of different length and repetitions could be achieved. The isolation of the different voltage stages is ensured by deep trenches and highly doped buried layers.

Scanning spreading resistance microscopy for failure analysis of nLDMOS devices with decreased breakdown voltage

Abstract Scanning Spreading Resistance Microscopy (SSRM) is successfully applied to investigate failing nLDMOS test devices that exhibit a lowered break down voltage (BVDSS) in electrical test. Cross-sectional, two-dimensional maps of the local sample resistivity from fail and reference (pass) devices reveal significant differences of the dopant concentration in individual, specific regions. This important information enables unambiguous identification of the root cause of the device failure to be dopant related. Furthermore, from a set of hypothesis, which explains the failed electrical test, SSRM results confirm exactly one and rule out the other. These are two important steps towards root cause identification. Since a relative comparison of fail and pass SSRM scans is sufficient for this failure analysis, an extensive data calibration for the absolute dopant concentration by means of additional SSRM measurements on test samples with known dopant concentration is not required. The ability of SSRM to prove or disprove miscellaneous fail hypothesis even without data calibration makes this method a very powerful tool for analysis of dopant related failure types.

Single pulse energy capability and failure modes of n- and p-channel LDMOS with thick copper metallization

Electro-thermal destruction of n- and p-channel lateral double-diffused MOS in smart power ICs is investigated by electrical pulse experiments, simulations and failure analysis. It was observed experimentally and by TCAD simulation that the location of the hot spot plays very important role for single pulse energy capability. Damage both in silicon and copper metallization was observed. The n-DMOS exhibits better energy capability compared to p-DMOS due to better cooling efficiency of silicon area by the copper metallization. Effect of drift region length, doping profile and of copper metal thickness on energy capability is also analyzed.