Rolf Weis

Challenges for the DRAM cell scaling to 40nm

This paper reviews the concepts, status and challenges for the DRAM scaling down to 40nm. The technologies that are discussed are the DRAM cell capacitor structures and materials, as well as the cell transistor structures

Trench DRAM Technologies for the 50nm Node and Beyond

This paper reviews the DRAM technology challenges for overcoming the 50nm barrier. First the product requirements and barriers to shrink the DRAM cell beyond 50nm will be addressed. Then the technology solutions for DRAM cell capacitor, cell transistor, and support transistors are presented. Key enablers arc high aspect ratio cell capacitor structures, new capacitor materials, 3-dimensional cell transistor schemes and high performance LSTP support device technologies