Ralf Rudolf

Key technologies for system-integration in the automotive and Industrial Applications

System integration and high power density of monolithic and multichip designs are the driving force for the progress in power electronic systems. The whole system has to be considered and optimized to meet this target and to keep the overall ruggedness, sensitivity toward electromagnetic interference and long term reliability, Silicon utilization system reliability and power units miniaturization are the key factors. In this paper new technologies, advanced devices concepts and future system aspect for system-integration in the automotive and industrial segments are discussed. In both fields of applications these are huge requirements toward system dynamic characteristic, overload capability, ruggedness behavior and reliability. In the automotive segment technologies working at high operating temperatures are required and in the industrial are high blocking voltage capabilities are needed.

Automotive 130 nm smart-power-technology including embedded flash functionality

In this paper a 130 nm BCD technology platform is presented. The process offers logic-devices, flash-devices and high voltage devices with rated voltages up to 60 V. There are HV analog devices with variable channel length and HV power devices with low on-resistances. To ensure the safe operation of the power devices, a superior robustness against high energetic pulses of different length and repetitions could be achieved. The isolation of the different voltage stages is ensured by deep trenches and highly doped buried layers.

Physical understanding and modelling of new hot-carrier degradation effect on PLDMOS transistor

Hot carrier injection, inducing source-drain current (IDS) increase in p-channel LDMOS transistors, is investigated. At low gate voltage (VGS) and high drain voltage (VDS), reduction of the on-resistance (RON) is observed [1, 5]. However, it has never been observed before, that the RON drift becomes constant after long stress time and the device resistance is not increased further afterwards. As soon as the RON almost reaches its constant level, the threshold voltage shift begins. The effect has been analyzed combining experimental data and TCAD simulations. For the first time recovery effect after hot carrier stress even at room temperature is reported.

Hot-carrier and recovery effect on p-channel lateral DMOS

Hot-carrier, inducing source-drain current (IDS) increase in high-voltage p-channel lateral DMOS (LDMOS) transistors, is investigated. At low gate voltage (VGS) and high drain voltage (VDS), electrons are injected into the gate oxide, creating negative fixed oxide charges and interface-states above the accumulation region and the channel towards the source side (Figure 1). The source drain current (Ids) increase leads to threshold voltage shift (Vth→0V) and for higher stress conditions a drain-source leakage can be observed. The effect has been analyzed combining experimental data and TCAD simulations. For the first time recovery effect after hot carrier stress even at low temperature is reported.

Experimental and Theoretical Analyses of the Electrical SOA of Rugged p-Channel LDMOS

Numerical TCAD and transmission line pulse analysis of an electrical safe operating area of a robust p-channel lateral DMOS transistor is performed. The observed independence of the trigger current on the applied gate-source voltage is attributed to a lack of quasi-saturation effect which is usually observed in an n-channel LDMOS. The dependence of the trigger voltage on the length of channel and drift regions is also analyzed, and the tradeoff with the specific on-resistance (RDSon) is given.

Scanning spreading resistance microscopy for failure analysis of nLDMOS devices with decreased breakdown voltage

Abstract Scanning Spreading Resistance Microscopy (SSRM) is successfully applied to investigate failing nLDMOS test devices that exhibit a lowered break down voltage (BVDSS) in electrical test. Cross-sectional, two-dimensional maps of the local sample resistivity from fail and reference (pass) devices reveal significant differences of the dopant concentration in individual, specific regions. This important information enables unambiguous identification of the root cause of the device failure to be dopant related. Furthermore, from a set of hypothesis, which explains the failed electrical test, SSRM results confirm exactly one and rule out the other. These are two important steps towards root cause identification. Since a relative comparison of fail and pass SSRM scans is sufficient for this failure analysis, an extensive data calibration for the absolute dopant concentration by means of additional SSRM measurements on test samples with known dopant concentration is not required. The ability of SSRM to prove or disprove miscellaneous fail hypothesis even without data calibration makes this method a very powerful tool for analysis of dopant related failure types.

Single pulse energy capability and failure modes of n- and p-channel LDMOS with thick copper metallization

Electro-thermal destruction of n- and p-channel lateral double-diffused MOS in smart power ICs is investigated by electrical pulse experiments, simulations and failure analysis. It was observed experimentally and by TCAD simulation that the location of the hot spot plays very important role for single pulse energy capability. Damage both in silicon and copper metallization was observed. The n-DMOS exhibits better energy capability compared to p-DMOS due to better cooling efficiency of silicon area by the copper metallization. Effect of drift region length, doping profile and of copper metal thickness on energy capability is also analyzed.