Marcello Dalpasso

Virtual simulation of distributed IP-based designs

JavaCAD, an Internet-based tool with a secure client-server architecture, lets designers perform functional simulation, fault simulation, and cost estimation of circuits containing IP components. It also ensures IP protection for both IP vendors and users, and provides seamless transition between IP evaluation and purchase.

Specification and validation of disstributed IP-based designs with JavaCAD

This paper presents JavaCAD, a new Java-based CAD framework for the design, validation and simulation of systems using third-party components with reciprocal intellectual property (IP) protection. The designer can use remote components with a dedicated and secure Internet protocol, that guarantees IP protection and supports a smooth transition between component evaluation and purchase.

Analysis of dynamic effects of resistive bridging faults in CMOS and BiCMOS digital ICs

This paper presents a study of the dynamic behavior of CMOS and BiCMOS digital circuits induced by bridging faults, whose resistance value is shown to have a strong impact on the dynamic behavior of faulty gates and of their fan-out gates. The problem of fault detection is addressed considering delay fault testing and results are compared with those achieved by means of functional testing. Electrical simulation has been used to investigate the main differences between BiCMOS and CMOS circuits. It is shown that, because of the large driving capability of BJTs, the detection as delay faults of bridging faults in BiCMOS circuits is more difficult than in the CMOS case.<<ETX>>

Parametric Bridging Fault Characterieation for the Fault Simulation of Library-Based ICs

This paper presents a new approach to the fault simulation of parametric bridgings in CMOS ICs synthesized by means of libraries of macro-gates. The method is based on a fast but accurate preliminary characterization of any macro-gate for each input set. Such a characterization provides all information to determine, during the actual fault simulation, the maximum value of resistance for any considered bridging that makes the fault observable at a circuit primary output. This library characterization is very general, and can be used with any fa.ult simulation technique. Results on several benchmarks show that this approach allows the fault simulation of internal parametric bridging faults in a time comparable to that of the classical line stuck-ats.

Bridging fault modeling and simulation for deep submicron CMOS ICs

Testing bridging faults in deep submicron CMOS digital ICs faces new problems because of pushing the technology limits. The growing dispersion of process parameters makes it hard to use conventional bridging fault models for high-quality testing. A new fault model is proposed to account for bridging faults in a way that is independent of electrical parameters and provides a significant coverage metric. Conditions are defined to ensure that (under steady-state conditions) either a fault is detected by a test sequence or it will not give rise to errors for any other input, independently of the actual values of IC parameters. Such a fault model has been implemented in a simulator and validated over combinational benchmarks.

Analysis of Steady State Detection of Resistive Bridging Faults in BiCMOS Digital ICs

This paper analyzes the effects induced on the electrical behavior of BiCMOS digital circuits by bridging faults, whose instrinsic resistance value is shown to have a strong impact on the static behavior of faulty gates and of their fan-out gates. The problem of fault detection is then addressed considering two different testing techniques (current monitoring and functional testing). Simulations of the electrical behavior of faulty BiCMOS circuits have enlightened the main differences with respect to the CMOS technology: the larger driving capability of BJTs with respect to MOSFETs makes the detection of bridging faults much more difficult in BiCMOS circuits when functional testing is considered, but more effective when current monitoring is used.

Hardware/software IP protection

Design methodologies based on reuse of intellectual property (IP) components critically depend on techniques to protect IP ownership. IP protection is particularly challenging for hardware/software systems, where an IP core runs embedded software: both the software and the core are valuable IP that must be protected. We propose a new technique for protecting the IP of both processor cores and application software in hardware/software systems. Our approach is based on public-key cryptography and it has been implemented as a package in the JavaCAD distributed design and simulation environment [1].

Self-learning signature analysis for non-volatile memory testing

A new BIST scheme suitable for on-chip testing of non-volatile memories and based on signature analysis is presented. The signature of the whole memory, whose content can be selectively changed by the user, is dynamically self-learned by the memory and it is saved in a dedicated memory location. Such a signature can be externally compared with the expected one in order to check for the programming operation, or it can be used for self-test when data retention must be checked.

Modeling of broken connections faults in CMOS ICs

This work presents a fault model to effectively account for broken connections inside CMOS circuits. The proposed model is very general, since it allows one to detect broken connections that cannot be individualized by means of test sequences for stuck-open faults; in addition, the detection of a broken connection in a node ensures the detection of all stuck-open faults of the transistors connected to that node. Conditions for the detection of broken connections are derived from electrical considerations and the minimum number of input vectors to be applied to test for a broken connection in a node is determined by graph theory. The model can be used to derive tests and to perform fault simulations independently of the actual layout of the circuit.<<ETX>>

High Quality Test Vectors for Bridging Faults in the Presence of IC's Parameters Variations

The growing dispersion of parameters in CMOS ICs poses relevant uncertainties on gate output conductances and logic thresholds that affect bridging fault (BF) detection. To analyze the quality of fault simulation and test generation tools using nominal IC parameters, we studied BF detection as a function of the standard deviation of parameters: results show that a single test vector cannot ensure acceptable escape probabilities. Conversely, the minimal number of test vectors providing null escape probability is upper-bounded with respect to variations of parameters, as verified by Monte Carlo electrical-level simulations. We propose a method to derive such minimal test sets for low frequency testing. A fault simulator and a test generator have been developed supporting the search of minimal test sets targeting a null escape probability.