Michele Favalli

Estimate of signal probability in combinational logic networks

Two methods for the calculation of node signal probabilities in combinational networks are presented. These techniques provide a better accuracy than existing algorithms and a deeper insight in the effects of first-order correlations due to multiple fan-out reconvergences. The proposed algorithms are shown to compare favorably with existing procedures in the analysis of significant benchmarks, both in accuracy and in computational efficiency.<<ETX>>

Self-checking detection and diagnosis of transient, delay, and crosstalk faults affecting bus lines

We present a self-checking detection and diagnosis scheme for transient, delay, and crosstalk faults affecting bus lines of synchronous systems. Faults that are likely to result in the connected logic sampling incorrect bus data are on-line detected. The position of the affected line(s) within the considered bus is identified and properly encoded. The proposed scheme is self-checking with respect to a realistic set of possible internal faults, including node stuck-ats, transistor stuck-ons, transistor stuck-opens, resistive bridgings, transient faults, delays and crosstalks.

Analysis of glitch power dissipation in CMOS ICs

Since a consistent fraction of the total power dissipated in CMOS ICs is due to glitches, power estimation tools should correctly account for their presence. This can be done at the electrical level but only for medium size circuits. The accuracy achievable at the logic level, instead, has not yet been analyzed in details. In this paper, the phenomenon of glitch power dissipation is analyzed at the electrical level showing the main sources of error in gate-level simulation (with di erent delay models) and providing basic guidelines for the development of adequate logic level models.

Aliasing in signature analysis testing with multiple input shift registers

An investigation of the properties of multiple input shift registers for signature analysis is presented. The assumption of independent errors at the register inputs has been used to model the register behavior as a Markov process whose equations have been solved to obtain the exact dependence of aliasing probabilities as a function of test length, input error probabilities, and feedback structure. Some unique featured of maximum-length registers are proven. Accurate simplified expressions of aliasing probability are derived for use as tools in the evaluation of the coverage. >

Novel design for testability schemes for CMOS ICs

The authors present ideas for addressing the problem of detecting non-stuck-at faults in CMOS circuits that cannot be revealed by means of conventional methods (i.e., as logical errors in the steady-state response). Two techniques are proposed for detecting analog faults, particularly those resulting in intermediate voltages along circuit branches due to faulty conductive paths between the power supply and ground. Involving the conversion of analog faults into stuck-ats and the use of distributed testing logic, these techniques are shown to avoid the drawbacks of previous solutions. A method is proposed for online detection of delay faults, so far not yet considered in the context of design-for-testability. All the proposed techniques require little extra hardware and lead to minimal performance degradations. >

Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture

This paper proposes a built-in self-test/self-diagnosis procedure at start-up of an on-chip network (NoC). Concurrent BIST operations are carried out after reset at each switch, thus resulting in scalable test application time with network size. The key principle consists of exploiting the inherent structural redundancy of the NoC architecture in a cooperative way, thus detecting faults in test pattern generators too. At-speed testing of stuck-at faults can be performed in less than 1200 cycles regardless of their size, with an hardware overhead of less than 11%.

An analytical model for the aliasing probability in signature analysis testing

The Markov chain model of linear feedback shift-registers (LFSRs) for signature analysis testing is analytically solved to obtain the exact expression of the aliasing error probability as a function of test length, error probability, and the structure of the feedback network. The dependence on feedback configuration is explored in depth, and it is proven that maximum-length LFSRs have the best performances with respect to aliasing, regardless of the particular structure of their feedback network. Simplified expressions of aliasing probability are also derived for use as practical tools to design LFSRs for IC signature analysis testing, and a heuristic criterion is given for the identification of peaks in aliasing probability. >

Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing

This paper analyses some of the most common error-detecting codes used in self-checking circuits with respect to the errors induced by crosstalk faults (CFs). The electrical-level behavior of circuits in the presence of CFs has been analyzed by considering these faults as parametric. A logic-level model providing the probability of errors has been abstracted and applied to the case of functional unit outputs (buses). Finally, the probability of detectable and undetectable errors has been evaluated for the parity, two-rail, m-out-of-n, and Berger codes, thus providing some design hint.

Testability measures in pseudorandom testing

The authors present two methods for computing the fault detection probabilities in combinational networks. The methods provide a deeper insight into the effects of signal correlations caused by multiple fan-out reconvergencies and can be used in testability analysis to predict the fault coverage of pseudorandom patterns. The performances of these algorithms have been tested on significant benchmarks and compare favorably with those of previous procedures. >

Fault simulation of unconventional faults in CMOS circuits

The authors present a novel technique to study the detection of non-stuck-at faults in CMOS circuits. Gate-level models of CMOS faults not yet adequately covered in the literature are developed. Suitable models for transistor stuck-open and stuck-on, gate-drain shorts, and bridgings are implemented in a fault simulator. Results obtained with typical circuits are presented and discussed to analyze the influence of circuit architecture and type of test vector (deterministic or pseudorandom) on the coverage of non-stuck-at faults. The following general conclusions are drawn from these results: (1) shorts between transistor gate and drain are adequately detected by stuck-at oriented test patterns, and, hence, they do not represent a significant problem in IC testing: (2) the coverage of transistors stuck-open is significantly dependent on the test pattern generation method used; (3) the detectability of bridgings depends strongly on the circuit topology; and (4) the indirect coverage of transistors stuck-on is inadequate, essentially because a large number of them are undetectable. >