Shawn G. Thomas

Bendable integrated circuits on plastic substrates by use of printed ribbons of single-crystalline silicon

This letter presents studies of several simple integrated circuits—n-channel metal-oxide semiconductor inverters, five-stage ring oscillators, and differential amplifiers—formed on thin, bendable plastic substrates with printed ribbons of ultrathin single-crystalline silicon as the semiconductor. The inverters exhibit gains as high as 2.5, the ring oscillators operate with oscillation frequencies between 8 and 9MHz at low supply voltages (∼4V), and the differential amplifiers show good performance and voltage gains of 1.3 for 500mV input signals. The responses of these systems to bending-induced strains show that relatively moderate changes of individual transistors can be significant for the operation of circuits that incorporate many transistors.

Characterization of nickel Germanide thin films for use as contacts to p-channel Germanium MOSFETs

We have measured the physical properties and resistivity of nickel germanide thin films formed by the rapid thermal annealing of nickel metal on p-type germanium substrates. Rutherford back scattering and high-resolution electron diffraction confirm that the stoichiometry of the resulting nickel germanide film corresponds to NiGe and has an orthorhombic unit cell with dimensions comparable to that of bulk samples. Transmission electron microscopy shows a poly-crystalline film structure with grain size > 0.1 /spl mu/m. The resistivity values for films annealed in the range 350/spl deg/C-500/spl deg/C are comparable to those of metal silicides. Measurements of the specific contact resistance suggest that values approaching 2 /spl times/ 10/sup -7/ /spl Omega/.cm/sup 2/ can be realized using NiGe formed on heavily doped p-type germanium.

Interdigitated Ge p-i-n photodetectors fabricated on a Si substrate using graded SiGe buffer layers

We report an interdigitated p-i-n photodetector fabricated on a 1-/spl mu/m-thick Ge epitaxial layer grown on a Si substrate using a 10-/spl mu/m-thick graded SiGe buffer layer. A growth rate of 45 /spl Aring//s/spl sim/60 /spl Aring//s was achieved using low-energy plasma enhanced chemical vapor deposition. The Ge epitaxial layer had a threading dislocation density of 10/sup 5/ cm/sup -2/ and a rms surface roughness of 3.28 nm. The 3-dB bandwidth and the external quantum efficiency were measured on a photodetector having 1-/spl mu/m finger width and 2-/spl mu/m spacing with a 25/spl times/28 /spl mu/m/sup 2/ active area. At a wavelength of 1.3 /spl mu/m, the bandwidth was 2.2, 3.5, and 3.8 GHz at bias voltages of -1, -3, and -5 V, respectively. The dark current was 3.2 and 5.0 /spl mu/A at -3 and -5 V, respectively. This photodetector exhibited an external quantum efficiency of 49% at a wavelength of 1.3 /spl mu/m.

Fabrication and modeling of gigahertz photodetectors in heteroepitaxial Ge-on-Si using a graded buffer layer deposited by low energy plasma enhanced CVD

Photodetectors were fabricated in a heteroepitaxial Ge-on-Si deposited by low energy plasma enhanced CVD. Dark current density of 4.6 nA//spl mu/m, 49 % quantum efficiency, and a -3 dB bandwidth of 3.5 GHz were measured at 1.3 /spl mu/m wavelength and -3 V bias. Numerical simulations predict device modifications can achieve 10 Gbps (/spl cong/ 7 GHz) bandwidth.

Fabrication and characterization of InGaP/GaAs heterojunction bipolar transistors on GOI substrates

In this letter, we report the first demonstration of InGaP/GaAs heterojunction bipolar transistors (HBTs) on germanium-on-insulator (GOI) substrates. We have performed physical characterization of the epitaxial layers to verify the high quality of the III-V epitaxial material grown on the GOI substrates and performed dc characterization of large-area InGaP/GaAs HBTs fabricated on the substrates. The InGaP/GaAs HBTs realized on GOI substrates were compared with identical devices grown on bulk germanium substrates and similar devices on semi-insulating GaAs substrates.

Selective Epitaxial Growth (SEG) of Highly Doped Si:P on Source/Drain Areas of NMOS Devices Using Si3H8/PH3/Cl2 Chemistry

In-situ doped Si:P alloys with high P concentration received much interest over the last few years as a method to reduce external transistor resistance (and contact resistance) [1-6]. An optimized Si3H8/PH3/Cl2 based Si:P SEG process with a SEG rate of ~25 nm/min developed on a 300 mm Epsilon reactor enables a 80-170s short deposition for typical epitaxial layers (35-70 nm), well suitable for high volume manufacturing (HVM) [7]. Different deposition strategies (co-flow vs. CDE), different Si containing precursors such as SiCl2H2, Si2Cl2H4, SiH4, Si2H6, Si3H8, Si4H10 and Si5H12, different etch precursors such as HCl, HBr and Cl2 as well as the use of inhibitors or catalysts had been considered [7-8]. Even at very low process temperatures (e.g. 500-550°C) the combination of Si3H8 and Cl2 offers high growth and etch rates, respectively, allowing very high [P] incorporation, very sharp doping transitions, and thanks to the low thermal budget very low dopant diffusion. The low thermal budget also preserves strain of other already incorporated strained layers (e.g. SiGe:B). Si:P SEG has been integrated on ETSOI, FinFET’s and into recessed S/D areas of partially depleted devices [9-15] and characterized by XSEM, TDSEM as well as SIMS. Electrical results from devices with integrated Si:P SEG will be presented elsewhere. The shape of the raised S/D areas on Si(100) can be tuned from entirely flat to (111) faceted (fig. 1) which reduces capacitance and improves the effectiveness of stressed liners [16]. Combining steps 3+4 of the NMOS process flow (fig.2), by integrating an isothermal in-situ removal of Si0.65Ge0.35 from the NMOS areas with a high etch rate selectivity against the 6-7 nm thin SOI at process temperature offers several advantages. Since, for this particular application, the SiGe protects the SOI surface the in-situ H2 prebake and the cool-down to process temperature can be eliminated, significantly reducing recipe overhead and the need for a separated, dedicated pre-clean module. For FinFET’s the reduction of parasitic resistance Rpara is a primary challenge [3-4]. To reduce Rpara an epitaxial S/D extension technique is required in such a way that the FinFET has wider body in the S/D extensions than in the channel portion. 3-D simulations [17] have shown that FinFET’s with diamond shaped epi (figs 3b + 4b) are superior to FinFET’s with flat epi overgrowth (figs 3a + 4a). As silicide gets closer to the fin and the interface between silicide and Si becomes larger, the area with higher current density spreads out [17]. Merged S/D with diamond shaped epi structure will be achievable down to the 11 nm node. The epi challenge is to grow on vertical Si(110) surfaces, where growth rate, etch rate and [P] incorporation differs. On partially depleted devices with recessed S/D areas (figs 5), the biggest difficultly stems from the fact that both, Si (100) and Si (110) surfaces are present simultaneously, very similar to SEG of SiCP [9-15]. We will show trends (sensitivity analysis) for growth rate and resistivity measured on bare pwafers as a function of the main process variables (Temperature, Si3H8, PH3 and Cl2 flows). We will further discuss the process performance of the Si3H8/Cl2 process with respect to chemical loading effects. References: [1] M. Bauer et al., Semicond. Sci. Technol. 22 (1) pp. S183-S187 (2007); [2] M. Bauer et al., ISTDM pp. 18-19 (2008); [3] T.Y. Liow et al, IEEE Trans. Electron Devices 55 (9) pp. 2475-2483 (2008) ; [4] E.-H. Toh et al, IEEE Electron Device Letters 29 (7) pp. 731-733 (2008); [5] S. Chopra et al., ECS Transactions 13 (1) pp. 307312 (2008); [6] M. Bauer US 7,687,383; [7] M. Bauer et al., ECS Transactions 13 (1) pp. 287-298 (2008); [8] M. Bauer et al., TSF 518 pp. S200-S203 (2010); [9] P. Grudowski et al., IEEE SOI Conf. Proc. pp. 17-18 (2007); [10] Z. Ren et al., Symp. VLSI Tech. 172-173 (2008); [11] F. Yang et al., ECS Transactions 16 (10) pp. 317-323 (2008); [12] M. Bauer et al., ECS Transactions 16 (10) pp. 1001-1013 (2008); [13] F. Yang et al., IEDM Tech. Dig. pp. 51-54 (2008); [14] P. Verheyen et al., IEEE Electron Device Letters 29 (11) pp. 1206-1208 (2008); [15] A. Dube et al., ECS Transactions 28 (1) pp. 63-71 (2010). [16] K. Cheng et al., IEDM Tech. Dig. pp. 49-52 (2009); [17] H. Kawasaki et al., IEDM Tech. Dig. pp. 289-292 (2009).

Cointegration of In Situ Doped Silicon–Carbon Source and Silicon–Carbon I-Region in P-Channel Silicon Nanowire Impact-Ionization Transistor

The p-channel impact-ionization nanowire multiple- gate field-effect transistors (I-MuGFETs or I-FinFETs), which have a multiple-gate/nanowire-channel architecture, were demonstrated. The superior gate-to-channel coupling reduces the breakdown voltage VBD for enhanced device performance. For the first time, an in situ doped source was incorporated with the impact-ionization MOS transistor. The in situ phosphorus-doped Si source with improved dopant activation and very abrupt junction profile reduces VBD and enhances the on-state current Ion. An additional improvement was also achieved by incorporating a strained Si1-yCy impact-ionization region (I-region) and an in situ doped Si1-yCy source, leading to reduction in Vbd and enhancement in Ion. This is due to strain-induced reduction of the impact-ionization threshold energy Eth. Furthermore, an excellent subthreshold swing of below 3 mV/decade at room temperature was achieved for all devices.

Throughput Considerations for In-Situ Doped Embedded Silicon Carbon Stressor Selectively Grown into Recessed Source Drain Areas of NMOS Devices

In this paper we calculate throughput based on recipe overhead (chamber etch, wafer load, wafer bake, cool down, unload) and deposition time for “true” SEG or the core cycle time (deposition, purge, etch, purge times) for a CDE process. In the latter case an average, effective growth rate (GR) can be extracted by dividing the deposited thickness per cycle by the cycle time. In high volume manufacturing (HVM) high SEG GR are necessary for high throughput and low Cost of Ownership (CoO). High GR also enable high substitutional carbon levels [C]sub in dilute Si:C alloys. In this work all experiments were exclusively performed using Silcore (ASM trademarked version of Si3H8). Due to the high GR at low process temperature, high [C]sub and low films resistivities can be obtained independent of the two different Cl containing etch chemistries that were used in this study. The main challenge of using Cl2 compared to the ASM proprietary etch chemistry is the 25-30 times lower etch rate selectivity (~7 vs. ~190) of α-SiCP over epi-SiCP. As a result of the low etch rate selectivity using a Cl2 etch chemistry, a significant portion of the epitaxial SiC:P is also etched with the α-SiCP. This results in a low effective growth rate which has a deleterious impact to throughput.

Characterization Techniques for Evaluating Strained Si CMOS Materials

The electron and hole mobility of Si complementary metal on oxide field effect transistors (CMOS) can be enhanced by introducing a biaxial tensile stress in the Si channel. This paper outlines several key analytical techniques needed to investigate such layers. Raman scattering is used to measure the strain in the Si channel as well as to map the spatial distribution of strain in Si at a lateral resolution better than 0.5 μm. Atomic force microscopy (AFM) is used to measure the surface roughness. Transmission electron microscopy (TEM) is used to reveal dislocations in the structure, the nature of the dislocations and the propagation of the dislocations. Secondary ion mass spectrometry (SIMS) is used to monitor the Ge content profile in the structure and the thickness of each layer. In the long term, inline nondestructive techniques are desired for epi‐monitoring in manufacturing. Two techniques, spectroscopic ellipsometry (SE) and x‐ray reflectivity (XRR), have shown promise at this stage.

Novel CVD Strategies and Novel Chemical Precursors Enabling Low Temperature Epitaxy of Si and Si:C Alloys

In this paper we will discuss non-traditional chemical precursors for carbon-doped Silicon (Si:C) that enable improved manufacturability through higher growth rates and new deposition temperature regimes commensurate with the drive to lower thermal budgets of integration CMOS and DRAM platforms. Among the precursors to be discussed are dichlorodisilane (DCDS; Si2Cl2H4), dichlorosilane (DCS) and Silcore (Si3H8).