Mariano Dissegna

Engineering optimal high current characteristics of high voltage DENMOS

This paper demonstrates the dramatic improvement in ESD performance of HV DENMOS and LDMOS obtained by using selective drain extension silicide blocking (SBLK). The results are validated through 3D TCAD and TLP measurements on different technologies. Measured D.C. Id-Vd characteristics show minimal performance impact due to the addition of SBLK region.

Prediction of Charged Device Model Peak Discharge Current for Microelectronic Components

This paper presents a computationally efficient methodology to predict the peak current stress experienced by a microelectronic component during a field-induced charge device model (FICDM) electrostatic discharge test. The methodology is applied to a variety of IC components in different types of packages; the peak current values obtained from simulations agree well with those obtained from FICDM measurements.

CDM circuit simulation of a HV operational amplifier realized in 0.35um smart power technology

CDM circuit simulations feasibility on complex smart power circuits is presented in this work and applied to a high voltage operational amplifier. Simulation results are validated by means of measurements on dedicated test circuits and failure analysis. Pre-requisites for simulations and device model improvements are deeply investigated by means of vf-TLP measurements.

Case study of DPI robustness of a MOS-SCR structure for automotive applications

This paper presents a case study to demonstrate that transient-triggered ESD protection circuits may fail the DPI automotive requirement. A novel scheme is devised to improve the DPI performance of a MOSSCR protection device while maintaining the system-level ESD performance.

Improving the long pulse width failure current of NPN in BiCMOS technology

The pulse width dependency of the failure current for NPN structures in a 0.18-μm BiCMOS technology is studied using measurements and TCAD simulation. The desired “Wunsch-Bell” behavior is not observed due to formation of current filaments in this device; however, the failure current for long pulse widths can be increased by layout changes.

Impact of sub-threshold SOA on ESD protection schemes

SOA (safe operating area) at subthreshold gate voltages are typically not of interest during normal operation. Under ESD conditions, however, the device could be biased in the subthreshold regime. In this paper we discuss the impact of subthreshold gate voltages on the SOA boundary of LDMOS devices and its implications to ESD design.