Marija Blagojevic

SOI capacitor-less 1-transistor DRAM sensing scheme with automatic reference generation

Recently, the new concept of the capacitor-less 1T DRAM cell has been developed. The memory cell (MC) using a single transistor on SOI exploits the Floating Body (FB) effect of partially depleted (PD) SOI devices. The memory state can be read through the drain current of the storage transistors, i.e. I/sub 0/ and I/sub 1/ respectively. To read the information stored in a 1T DRAM cell, the current of the selected MC is compared to I/sub ref/ . In this paper, we propose a sensing method with automatic reference generation for SOI capacitor-less 1T DRAM. An adjustable current source is implemented as reference current source in order to sense the MC state. A digital-to-analog converter (DAC) and a successive approximation algorithm perform the calibration of I/sub ref/.

SOI Hall-Sensor Front End for Energy Measurement

The growing demand for the solid-state meters for power and energy measurement leads to the fully integrated Hall-sensor-based microsystem solutions. In this paper, a silicon-on-insulator (SOI) Hall-sensor-based microsystem for energy measurements with dynamic offset cancellation was described. The Hall sensor is used to multiply the line voltage and the line current, giving an output voltage proportional to the instantaneous power. Furthermore, the voltage at the Hall output is proportional to the line active power and can be further processed. By converting the sensor output voltage to a digital signal using a delta-sigma (DeltaSigma) modulator followed by a digital filtering, the energy consumption is observed at the end of the processing chain. The entire microsystem has been integrated in an experimental 0.5-mum fully depleted SOI process and has a measured output error of less than plusmn1.5%

SOI Hall sensor based solid state meter for power and energy measurements

Growing demand for the solid state meters for power and energy measurement leads to the fully integrated Hall sensor based microsystem solutions. In this paper we describe fully integrated SOI Hall sensor based microsystem for power and energy measurements with dynamic offset cancellation. Since Hall sensor behaves like a natural four quadrant multiplier it is used to multiply the line voltage and current giving the output voltage proportional to the instantaneous power. Furthermore, voltage at the Hall output is proportional to the line active power and can be further processed. By converting the sensor output voltage to digital signal using a sigma-delta demodulator followed by digital filtering, the energy consumption is observed at the end of the processing chain. The entire microsystem has been designed for high linearity and resolution, and integrated in 0.5 /spl mu/m FD SOI process.

FD SOI Hall sensor electronics interfaces for energy measurement

This paper presents a SOI Hall sensor based microsystem for energy measurement. The mixed-mode signal circuitry has been entirely designed and integrated in the experimental 0.5@mm fully depleted SOI 3V technology. It consists of an integrated Hall element, chopper stabilized sensor bias system, analog front end and digital back end. Aiming at performing accurate measurements, we have implemented a high linearity analog front end, as well as a high-resolution analog-to-digital conversion technique. Two versions of the microsystem have been realized. The first test chip contains a classical instrumentation amplifier as sensor amplifier, whereas the second one contains a linearized differential-difference amplifier as sensor amplifier. Both microsystems are fully functional and permits one to perform the measurements with an overall system error that is less than +/-1.5%.

Design Methodology Based On The Analog Blocks Retargeting From Bulk To FD SOI Using EKV Model

This paper presents a methodology of a basic analog blocks retargeting from bulk to fully depleted (FD) SOI technology. The design methodology is generally not related to the model used for the circuit simulations. However, the proposed one is closely linked to the EKV MOS model that has been chosen for the FD SOI circuit simulations. Same of EKV parameters are used and expressions along with the gm/I Ddesign approach to demonstrate that the basic analog circuits are simply retargeted from bulk to SOI

Microelectronic system for Hall sensor power measurements

A new integrated architecture for power measurements is proposed. The system includes the Hall sensor bias circuit and its front-end voltage amplifier. The implemented architecture performs the conversion of the electrical power into a Hall voltage, which is then amplified by a Differential Difference Amplifier (DDA). The architecture shows low power consumption and an optimized area however its resolution is drastically limited by the sensor offset and the linearity of the DDA. In order to achieve higher resolution, a second system is also proposed where a dynamic offset cancellation is employed in the bias scheme in order to reduce both the sensor and the electronics offset. To improve the sensor amplifier stage, a linearized version of the DDA is used. The latter architecture appears to be very promising and a linearity of 16-bit is achieved. Both simulations and measurements results from the comparison between the two architectures are shown in this paper.