Mark Clements

Clock distribution using cooperative ring oscillators

This paper presents a new form of integrated ring oscillator, the Cooperative Ring Oscillator (CRO), in which the controllable delay elements are distributed throughout a VLSI chip. Specifically, each stage of the CRO consists of many electrically parallel delay elements that are spatially distributed. The high degree of parallelism in the CRO provides strong signal aggregation that significantly reduces the skew within each clock phase. The CRO performs both clock generation and clock delivery, thus unifying the tasks of the oscillator, clock buffers, and distribution network into a single circuit. The strength of the CRO technique is that it can deliver multiple, low-skew clock phases to all areas of a large VLSI device at a cost in chip resources comparable to that of current single-phase clock distribution techniques. This strength creates the opportunity for system designers to make extensive use of multi-phase logic techniques to improve system performance.

An implantable neuro-stimulator device for a retinal prosthesis

In retina pigmentosa and macular degeneration, the photoreceptor cells of the retina (rods and cones) fail to respond to light. However, the discovery that direct electrical stimulation of retinal neurons can create visual sensation in patients inspires an electronic prosthesis which bypasses the defective photoreceptors. A prosthetic system is conceptually illustrated. A prototype implantable power and data receiver and neural stimulator, 4.6/spl times/4.7 mm/sup 2/ in 1.2 /spl mu/m CMOS, can drive a 10/spl times/10 array of retinal electrodes at real-time visual rates. The prototype serves two major goals. The first is to demonstrate the wireless transfer of power and data required for an implantable prosthesis. The second is to serve as a flexible stimulus waveform generator.

An implantable power and data receiver and neuro-stimulus chip for a retinal prosthesis system

In certain diseases of the retina, the photoreceptor cells do not respond to light and thus cause blindness. We describe an electronic retinal prosthesis system that can provide some vision to patients by direct electrical stimulation of the retinal neurons. Power and image data are transferred to the implanted stimulator through a wireless inductive link. The system consists of an external video camera with image processing and encoding hardware and a power and data transmitter. Implanted in the eye are power and data receivers, stimulus circuits, and electrode array. The most recent prototype implant device, implemented in 1.2 micron CMOS, implements demodulation and decoding of the data stream and produces biphasic current stimulus pulses for an array of 100 retinal electrodes at video frame rates.

Self-calibrating clock distribution with scheduled skews

This paper presents a self-calibrating clock distribution scheme that dynamically compensates manufacturing and environmental variations to minimize unintentional clock skews and employs non-zero intentional skews to improve system performance. The tracking process is implemented with an all-digital phase-locked loop and has been verified through a prototype chip. Test results confirm the theoretical predictions that the absolute value of unintentional skew is limited to /spl Delta/, which is the resolution of the sampling and compensation circuitry.

An epi-retinal visual prosthesis implementation

Retinitis pigmentosa and age-related macular degeneration leads to blindness through progressive loss of retinal photoreceptors. This paper describes an epi-retina visual prosthesis intended to provide electrical stimulation of the remaining, post-degenerative retina in order to recover some useful vision. The system includes extraoccular image acquisition and processing, a telemetry link based on inductive coupling, and an implantable neuro-stimulator for retina stimulation.

A technique for high-speed, fine-resolution pattern generation and its CMOS implementation

This paper presents an architecture for generating a high-speed data pattern with precise edge placement (resolution) by using the matched delay technique. The technique involves passing clock and data signals through arrays of matched delay elements in such a way that the data rate and resolution of the generated data stream are controlled by the difference of these matched delays. This difference can be made much smaller than an absolute gate delay. Since the resolution of conventional designs is determined by these absolute delays, the matched delay technique yields a much finer resolution than traditional methods and, in addition, generates high data rate patterns without the need of a high-speed clock. The matched delay technique lends itself to high-precision and high-speed applications such as fast network interfaces or test pattern generators. This paper also describes a matched delay data generator submitted for fabrication in a MOSIS 1.2 /spl mu/m CMOS technology. This implementation used biased delay elements to internally compensate for temperature and process variations. Simulations indicate the implementation described in this paper can generate data signals with on-chip bit rates of 833 Mb/s and resolutions of 100 ps.

Convolution, deconvolution, and mean field annealing suitable for analog VLSI

We formulate several standard digital image processing operations as circuits suitable for implementation in real-time analog VLSI, including nonlinear piecewise-constant image restoration using mean field annealing as a global optimization technique. We report test results from an imaging chip that performs user-controlled convolution of the image. We use simulated results for mean field annealing (MFA) in SPICE to show that deconvolution could be implemented by rearranging the subcircuits that perform the corresponding convolution. We report the results of realizing deconvolution in this way on a printed circuit board.

High speed, fine resolution pattern generation using the matched delay technique

This paper presents an architecture for generating a high-speed data pattern with precise edge placement (resolution) by using the matched delay technique. The technique involves passing clock and data signals through arrays of matched delay elements in such a way that the data rate and resolution of the generated data stream are controlled by the difference of these matched delays. This difference can be made much smaller than an absolute gate delay. Since the resolution of conventional designs is determined by these absolute delays, the matched delay technique yields a much finer resolution as well as higher speeds than traditional methods. The matched delay technique lends itself to high-precision and high-speed applications such as fast network interfaces or test pattern generators. This paper also describes a matched delay data generator submitted for fabrication in a MOSIS 1.2 /spl mu/m CMOS technology. Simulations indicate that data signals with on-chip bit rates of 833 Mb/s and resolutions of 100 ps can be generated.