Mark D. Jacunski

A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns

A family of embedded DRAMs which are fabricated in 45nm SOI technology is presented. The fast eDRAM has 64 b/BL and achieves a random cycle time of 1.3ns for VDD = 1.00V and typical process. The dense eDRAM has 128 b/BL and operates in multi-bank modes up to 1.67GHz for VDD = 1.0V and nominal process. The staggered - folded BL architecture with BL twisting over both the array and SAs is described as well as a novel wordline timer which generates a 75% duty cycle signal from a 50% duty cycle clock.

Embedded DRAM in 45-nm Technology and Beyond

As power and density requirements for embedded memories grow, products ranging from mobile applications to high-performance microprocessors are increasingly looking toward eDRAM as an alternative to SRAM. This article describes the state of the art in eDRAM architecture and design with a particular focus on test challenges and solutions.

A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST

An embedded DRAM macro fabricated in 65 nm CMOS achieves 1.0 GHz multi-banked operation at 1.0 V yielding 584 Gbits/sec. The array utilizes a 0.1 1 mum2 cell with 20 fF deep trench capacitor and 2.2 nm gate oxide transfer gate. Concurrent refresh allows for high availability via a second bank address. At-speed test and repair is accomplished with a new hierarchical BIST architecture. Measured random cycle time exceeds 333 MHz at 1.0 V with functional operation from 750 mV to 1.5 V and densities up to 36.5 Mbits.

In-situ measurement of variability in 45-nm SOI embedded DRAM arrays

A technique for in-situ measurement of process variation in deep trench capacitance, bitline capacitance, and device threshold voltage in embedded DRAM arrays is presented. The technique is used to directly measure the parameter statistics in two product representative 45-nm SOI eDRAM arrays.