Mark R. Plagens
Honeywell
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Publication
Featured researches published by Mark R. Plagens.
IEEE Journal of Solid-state Circuits | 1988
Andrzej Peczalski; Gary M. Lee; William R. Betten; H. Somal; Mark R. Plagens; James R. Biard; Ian Burrows; Barry K. Gilbert; Rick L. Thompson; Barbara Naused; Susan M. Karwoski; Mark L. Samson; Sharon K. Zahn
A 12*12 multiplier consisting of 19000 devices was successfully implemented on a 6000-gate array. A high-yield-oriented circuit design and the gate-array architecture are presented. It is shown that when temperature compensation is applied the GaAs circuit operating range can be extended over 160 degrees C range. The backgating and dynamic (switching) noise are also discussed as the key noise-margin limiting factors. A specialized on-chip circuitry which enables on-chip measurement and fault localization in complex GaAs ICs is proposed and implemented. The high yield of the multiplier (10%) seems to be limited only by particle contamination, which indicates that the noise margin is satisfactory for the GaAs nonselfaligned depletion-mode fabrication process. >
Archive | 2001
Mark R. Plagens; Michael J. Haji-Sheikh; Walter T. Matzen
Archive | 1994
James D. Cook; Albert W. Drabowicz; D. Joseph Maurer; Mark R. Plagens; Uppili Sridhar; Carl Stewart
Archive | 1996
Mark R. Plagens
Archive | 1991
Mark R. Plagens
Archive | 2001
Michael J. Haji-Sheikh; Mark R. Plagens; Robert Kryzanowski
Archive | 1993
Richard A. Davis; Mark R. Plagens; Uppili Sridhar
Archive | 2001
Mark R. Plagens
Archive | 1986
Mark R. Plagens
Archive | 2000
Richard Kirkpatrick; Mark R. Plagens
