Mark S. Chang

Simplified dual damascene process for multi-level metallization and interconnection structure

Method of decreased interlayer dielectric constant in a multilayer interconnect structure to increase device speed performance

Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS

Processing techniques for achieving production-worthy, low dielectric, low dielectric, low interconnect resistance and high performance IC

Polymer memory device formed in via opening

Methods of forming passive layers in organic memory cells

PROCESS FOR FABRICATING AN INTEGRATED CIRCUIT WITH A SELF-ALIGNED CONTACT

RELACS shrink method applied for single print resist mask for LDD or buried bitline implants using chemically amplified DUV type photoresist

Formation of STI (shallow trench isolation) structures within core and periphery areas of flash memory device

Process for fabricating high density memory cells using a polysilicon hard mask