Mark Sweet

Design and implementation of the POWER5 microprocessor

POWERS offers significantly increased performance over previous POWER designs by incorporating simultaneous multithreading, an enhanced memory subsystem, and extensive RAS and power management support. The 276M transistor processor is implemented in 13Onm silicon-on-insulator technology with 8-level of Cu metallization and operates at >1.5 GHz

Design and implementation of the POWER5/spl trade/ microprocessor

POWER5/sup TM/ is the next generation of IBMs POWER microprocessors. This design, sets a new standard of server performance by incorporating simultaneous multithreading (SMT), an enhanced distributed switch and memory subsystem supporting 164w SMP, and extensive RAS support. First pass hardware using IBMs 130nm silicon-on-insulator technology operates above 1.5GHz at 1.3V. POWER5s dual-threaded SMT creates up to two virtual processors per core, improving execution unit utilization and masking memory latency. Although a simplistic SMT implementation promised /spl sim/20% performance improvement, resizing critical microarchitectural resources almost doubles in many cases the SMT performance benefit at a 24% area. Implementing these microarchitectural enhancements posed challenges in meeting the chips frequency, area, power, and thermal targets.

A 1.2 W 66 MHz superscalar RISC microprocessor for set-tops, video games, and PDAs

This 32 b superscalar processor, having 18 mW/MHz projected power consumption at 66 MHz, is designed for desktop companions and high-end embedded multimedia applications with graphics-intensive requirements such as high-performance video games. This processor, the latest member of the PowerPC microprocessor family, can also be used in other low-power computing applications. The processor is fabricated in a 3.3 V, 0.5 m, 4-level metal CMOS resulting in 1 M transistors in a 7.07/spl times/7.07 mm/sup 2/ chip. Dual 4 kB instruction and data caches coupled to a high-performance 64 b multiplexed bus and separate execution units (float, integer, branch, and load-store) result in 2 instructions per clock cycle peak rate. Low-power design includes dynamically-powered-down execution units. Standby power is <2 mW. CPU to bus clock ratios of 2/spl times/ and 3/spl times/ allow control of system power while maintaining processor performance.