James K. Schaeffer

Contributions to the effective work function of platinum on hafnium dioxide

The intrinsic and extrinsic contributions to Fermi level pinning of platinum (Pt) electrodes on hafnium dioxide (HfO2) gate dielectrics are investigated by examining the impact of oxygen and forming gas anneals on the effective work function of Pt-HfO2-silicon capacitors. The effective platinum work function is ∼4.6eV when annealed in forming gas. However, diffusion of oxygen to the Pt∕HfO2 interface increases the platinum work function to a value of ∼4.9eV. Subsequent annealing in forming gas returns the platinum work function to a value comparable to that measured prior to the oxygen anneal. The effective platinum work functions are compared to the prediction of the metal induced gap states (MIGS) model. The presence of interfacial oxygen vacancies or platinum–hafnium bonds is believed to be responsible for a degree of pinning that is stronger than predicted from the MIGS model alone.

Challenges for the integration of metal gate electrodes

Integration challenges for metal gate electrodes including the presence of Fermi level pinning and the impact of interface chemistry on the effective metal work function are discussed. Gate stack thermal instabilities are explored, and for the first time results using tantalum-carbon based electrodes are presented.

Impact of Zr addition on properties of atomic layer deposited HfO2

The impact of Zr addition on microstructure of HfO2 after high temperature processing was investigated using Rutherford backscattering, x-ray diffraction (XRD), transmission electron microscopy, and atomic force microscopy (AFM). The ZrO2 content in the films was varied from ∼25% to 75%. XRD analysis shows that adding >50% ZrO2 leads to partial stabilization of tetragonal phase of the HfxZr1−xO2 alloy. AFM images revealed smaller grains with Zr addition. Conducting AFM showed more uniform and tighter tunneling current distribution in HfxZr1−xO2 compared to HfO2. Constant capacitance-voltage stressing performed on HfO2 and HfxZr1−xO2 metal-oxide-semiconductor capacitors indicated reduced charge trapping with Zr addition.

Tantalum carbonitride electrodes and the impact of interface chemistry on device characteristics

The intent of this research is to understand the role of interface chemistry on the effective work function and device characteristics of metal gate electrodes on hafnium dioxide (HfO2) gate dielectrics in metal oxide semiconductor field effect transistors. Since multiple factors, including crystal structure, preferred orientation, chemical composition, interface bonding, and reactions or interdiffusions, impact the effective work function, solid-solution carbonitrides of tantalum (TaCxN1−x) have been studied in an attempt to isolate the role of interface chemistry on the effective work function. Tantalum carbonitride films have been carefully deposited with similar Ta∕(C+N) ratios to understand how the substitution of N for C on the octahedral interstice in a face-centered-cubic tantalum lattice impacts device performance. Results indicate that the effective work function and device threshold voltage are reduced when the less electronegative carbon atom is substituted for the more electronegative nitroge...

Improved short channel device characteristics with stress relieved pre-oxide (SRPO) and a novel tantalum carbon alloy metal gate/HfO/sub 2/ stack

Threshold voltage instability is a critical problem for high-K dielectric implementation. This problem is much more serious for short channel devices due to process induced gate edge damage. A novel stress relieved pre-oxide (SRPO) followed by ALD of HfO/sub 2/ reduces the local charge density near the gate edge and short channel threshold voltage instability. Excellent cross wafer CETinv uniformity is achieved for the SRPO process. A new tantalum carbon alloy metal gate achieves a lower Vtsat than TaSiN gated devices due to a lower work function. Compared to HfO/sub 2//TaSiN devices using standard RCA pre-clean, HfO/sub 2//tantalum carbon alloy metal gate stack using the novel SRPO demonstrates a 3/spl times/ smaller Vt shift for short channel devices and a 16% Ion/Ioff improvement.

Improved Electrical Properties of ALD

The impact of ultrathin metal underlayer on physical and electrical properties of Hf<i> _x </i>Zr_1- <i> _x </i>O₂(x=~0.4) after high-temperature processing was investigated. An ~5-Aring Zr, ~5-Aring Hf, ~10-Aring Hf metal layer was sputter deposited prior to Hf<i> _x </i>Zr_1- <i> _x </i>O₂ growth. Cross-sectional transmission electron microscopy and secondary ions mass spectrometry analysis confirmed no Zr or Hf silicide formation between the high-<i>k</i> film and Si substrate even after 1000degC processing. No significant increase in equivalent oxide thickness or gate leakage current is observed on devices with metal underlayer. Furthermore, devices with a 5-Aring-thick Zr underlayer exhibited lower threshold voltage, higher mobility, and improved charge trapping characteristics.

\hbox{Hf}_{x} \hbox{Zr}_{1 - x}\hbox{O}_{2}

CMOS devices with high-k/metal gate stacks have been fabricated using a gate-first process flow and conventional stressors at gate lengths of 25 nm, highlighting the scalability of this approach for high performance SOI CMOS technology. AC drive currents of 1630muA/mum and 1190muA/mum have been demonstrated in 45 nm ground-rules at 1V and 200nA/mum off current for nFETs and pFETs, at a Tinv of 14 and 15 respectively. The drive currents were achieved using a simplified high-k/metal gate integration scheme with embedded SiGe and dual stress liners (DSL) and without utilizing additional stress enhancers. Devices have been fabricated with Tinvs down to 12 and 10.5 demonstrating the scalability of this approach for 32 nm and beyond.

Dielectrics Deposited on Ultrathin PVD Zr Underlayer

TaCy has been reported to have the appropriate work function for negative metal-oxide semiconductor metal in high-k metal-oxide field-effect transistors. As device size continues to shrink, a conformal deposition for metal gate electrodes is needed. In this work, we report on the development and characterization of a novel TaCy process by atomic layer deposition (ALD). Detailed physical properties of TaCy films are studied using ellipsometry, a four-point probe, Rutherford backscattering spectrometry (RBS), x-ray photoelectron spectroscopy (XPS), and x-ray diffraction (XRD). RBS and XPS analysis indicate that TaCy films are near-stoichiometric, nitrogen free, and have low oxygen impurities. Powder XRD spectra showed that ALD films have a cubic microstructure. XPS carbon bonding studies revealed that little or no glassy carbon is present in the bulk of the film. Excellent electrical properties are obtained using ALD TaCy as a metal gate electrode. Well-behaved capacitance-voltage characteristics with ALD H...

Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate

Factors responsible for the undesirably high values of positive-channel (p-channel) threshold voltage (Vt) in high-κ metal oxide semiconductor transistors are investigated. In silicon/silicon dioxide/hafnium dioxide/metal gate transistors an anomalous nonlinear relationship between the equivalent oxide thickness (EOT) and Vt occurs when the silicon dioxide (SiO2) interface layer is sufficiently thin (<2.3 nm). The deviation from the expected EOT versus Vt behavior is shown to be related to processing temperature, metal work-function, substrate doping type, and thickness of the high-κ material. This result, coupled with charge trapping measurements on samples with different SiO2 interface layer thickness, suggests that the loss of negative fixed charge via the tunneling of trapped electrons to the substrate is a possible explanation for the elevated p-channel Vt.

Atomic layer deposited TaCy metal gates: Impact on microstructure, electrical properties, and work function on HfO2 high-k dielectrics

Using a novel fluorinated TaxCy/high-k gate stack, we show breakthrough device reliability and performance improvements. This is a critical result since threshold voltage instability may be a fundamental problem and performance degradation for high-k is a concern. The novel fluorinated gate stack device exceeds the PBTI and NBTI targets with sufficient margin and has electron mobility comparable to the best polySi/SiON device on bulk Si reported so far