Rama I. Hegde

Thermodynamic stability of high-K dielectric metal oxides ZrO2 and HfO2 in contact with Si and SiO2

We present theoretical and experimental results regarding the thermodynamic stability of the high-k dielectrics ZrO2 and HfO2 in contact with Si and SiO2. The HfO2/Si interface is found to be stable with respect to formation of silicides whereas the ZrO2/Si interface is not. The metal–oxide/SiO2 interface is marginally unstable with respect to formation of silicates. Cross-sectional transmission electron micrographs expose formation of nodules, identified as silicides, across the polycrystalline silicon/ZrO2/Si interfaces but not for the interfaces with HfO2. For both ZrO2 and HfO2, the x-ray photoemission spectra illustrate formation of silicate-like compounds in the MO2/SiO2 interface.

Evidence of aluminum silicate formation during chemical vapor deposition of amorphous Al2O3 thin films on Si(100)

Using narrow nuclear reaction resonance profiling, aluminum profiles are obtained in ∼3.5 nm Al2O3 films deposited by low temperature (<400 °C) chemical vapor deposition on Si(100). Narrow nuclear resonance and Auger depth profiles show similar Al profiles for thicker (∼18 nm) films. The Al profile obtained on the thin film is consistent with a thin aluminum silicate layer, consisting of Al–O–Si bond units, between the silicon and Al2O3 layer. Transmission electron microscopy shows evidence for a two-layer structure in Si/Al2O3/Al stacks, and x-ray photoelectron spectroscopy shows a peak in the Si 2p region near 102 eV, consistent with Al–O–Si units. The silicate layer is speculated to result from reactions between silicon and hydroxyl groups formed on the surface during oxidation of the adsorbed precursor.

Fermi-level pinning at the polysilicon/metal-oxide interface-Part II

We report here that Fermi pinning at the polysilicon/metal-oxide interface causes high threshold voltages in MOSFET devices. In Part I, we investigated the different gatestack regions and determined that the polysilicon/metal oxide interface plays a key role on the threshold voltages. Now in Part II, the effects of the interfacial bonding are examined by experiments with submonolayer atomic-layer deposition (ALD) metal oxides and atomistic simulation. Results indicate that pinning occurs due to the interfacial Si-Hf and Si-O-Al bonds for HfO/sub 2/ and Al/sub 2/O/sub 3/, respectively. Oxygen vacancies at polysilicon/HfO/sub 2/ interfaces also lead to Fermi pinning. This fundamental characteristic affects the observed polysilicon depletion.

Growth and surface chemistry of oxynitride gate dielectric using nitric oxide

Oxynitride films grown on preoxidized (100) silicon surfaces in a nitric oxide (NO) ambient at 950 °C have been investigated using x‐ray photoelectron spectroscopy (XPS), secondary ion mass spectrometry (SIMS), atomic force microscopy (AFM), and cross‐sectional transmission electron microscopy (XTEM). Compared to N2O oxynitride, NO oxynitride exhibits very different surface chemistry, interface properties, and growth mechanisms. The etch back of NO and N2O oxynitride films allows control of sample thickness for the XPS measurements. NO oxynitride has the interfacial nitrogen (Nint) sharply peaked on the Si substrate side of the interface, while it is broad and on the dielectric side of the interface for the N2O oxynitride. The N(1s) XPS results reveal a clear distinction between N2O oxynitride and NO oxynitride. Near the Si/dielectric interface the NO oxynitride shows primarily Si≡N bonds, while the N2O films showed a N(1s) binding energy peak that is in‐between that of Si≡N bonds and Si2=N—O bonds. Furth...

Effects of anneal ambients and Pt thickness on Pt/Ti and Pt/Ti/TiN interfacial reactions

Using x‐ray diffraction, Rutherford backscattering spectrometry, Auger electron spectroscopy, and scanning electron microscopy, effects of ambient anneal and Pt thickness on the interdiffusion of Pt/Ti bilayers deposited on SiO2/Si and on reactively sputtered TiN/Ti/Si substrates have been investigated. The Pt layer was 2000 or 930 A thick while the Ti thickness was fixed at 1000 A. The wafers were annealed in either O2 or N2 ambients or in N2 followed by O2, with temperatures ranging from 600 to 800 °C for 30 min. The anneal ambients and the thickness of Pt relative to the Ti layer had tremendous effects on the interdiffusion processes, the reaction products, and the surface morphology of the multilayer structures. Samples annealed in O2 were generally rough, with bumps of the order of 1000 A, while those annealed in N2 were relatively smooth. With lead zirconium titanate on top, the surface of Pt/Ti electrode annealed in O2 at 650 °C was relatively smooth.

Fermi level pinning at the polySi/metal oxide interface

We report here for the first time that Fermi pinning at the polySi/metal oxide interface causes high threshold voltages in MOSFET devices. Results indicate that pinning occurs due to the interfacial Si-Hf and Si-O-Al bonds for HfO/sub 2/ and Al/sub 2/O/sub 3/, respectively. This fundamental characteristic also affects the observed polySi depletion. Device data and simulation results will be presented.

Hafnium zirconate gate dielectric for advanced gate stack applications

We report on the development of a hafnium zirconate (HfZrO4) alloy gate dielectric for advanced gate stack applications. The HfZrO4 and hafnium dioxide (HfO2) films were formed by atomic layer deposition using metal halides and heavy water as precursors. The HfZrO4 material properties were examined and compared with those of HfO2 by a wide variety of analytical methods. The dielectric properties, device performance, and reliability of HfZrO4 were investigated by fabricating HfZrO4/tantalum carbide (TaxCy) metal-oxide-semiconductor field effect transistor. The HfZrO4 dielectric film has smaller band gap, smaller and more uniform grains, less charge traps, and more uniform film quality than HfO2. The HfZrO4 dielectric films exhibited good thermal stability with silicon. Compared to HfO2, the HfZrO4 gate dielectric showed lower capacitance equivalent thickness value, higher transconductance, less charge trapping, higher drive current, lower threshold voltage (Vt), reduced capacitance-voltage (C-V) hysteresis...

Challenges for the integration of metal gate electrodes

Integration challenges for metal gate electrodes including the presence of Fermi level pinning and the impact of interface chemistry on the effective metal work function are discussed. Gate stack thermal instabilities are explored, and for the first time results using tantalum-carbon based electrodes are presented.

Relationship between growth conditions, nitrogen profile, and charge to breakdown of gate oxynitrides grown from pure N2O

We studied the relationship between the growth conditions, the nitrogen profile, and the charge to breakdown of N2O oxynitrides grown in a RTP and in a conventional furnace. RTP oxynitride shows nitrogen accumulation at the Si/SiO2 interface. On the other hand, furnace oxynitride shows almost uniform nitrogen distribution in the bulk, resulting in poor charge to breakdown characteristics. We find that two‐step oxynitridation processes provide nitrogen accumulation at the Si/SiO2 interface and result in better electrical properties than those of one‐step oxynitrides.

Compatibility of polycrystalline silicon gate deposition with HfO2 and Al2O3/HfO2 gate dielectrics

Polycrystalline-silicon (poly-Si) gate compatibility issues with HfO2 and Al2O3 capped HfO2 gate dielectrics are reported. It can be generally stated that chemical vapor deposition (CVD) silicon gates using silane deposited directly onto HfO2 results in electrical properties much worse compared to similar HfO2 films using platinum metal gates. However, depositing CVD silicon gates directly onto Al2O3 capped HfO2 showed greater than a 104 times reduction in gate leakage compared to the poly-Si/HfO2 and poly-Si/SiO2 controls of similar electrical thickness.