Tero Nieminen

An 1.2V 440-MS/s 0.13-µm CMOS pipelined Analog-to-Digital Converter with 5-8bit mode selection

In this paper, an 8-bit (with 5-8bit mode selection), 440-MS/s pipelined Analog-to-Digital Converter (ADC) is presented. The ADC utilizes double-sampling in order to relax the operational amplifier (opamp) settling time requirements. Redundant sign digit (RSD) correction compensates offset errors of the comparators. The ADC is designed with a 0.13-µm CMOS process. In the 8-bit mode, measured effective number of bits (ENOB) of the ADC is 6.10 with 162-MHz full-scale input, while the current drawn from 1.2V supply is 83mA.

A configurable sampling rate converter for all-digital 4G transmitters

This paper presents a digital interpolation chain for non-integer variable-ratio sampling rate conversion, targeted to 4G mobile applications. Such a system is needed in all-digital transmitters, where the sampling rate of the digital input to the RF front-end must be an integer fraction of the carrier frequency. A highly configurable architecture is proposed to cope with the flexibility needed in 4G applications. The system achieves excellent ACLR of 75 dB, EVM degradation of 0.05%, and RX-band noise below -160 dBc/Hz. Digital synthesis of the circuit in a 40nm low-power CMOS process results in a core area of only 0.073 mm2. The estimated power consumption is between 6 and 29 mW, depending on channel bandwidth and transmission band.

Analog baseband chain with analog to digital converter (ADC) of Synthetic Aperture Radar (SAR) receiver

An analog baseband chain together with an analog to digital converter (ADC) for a Synthetic Aperture Radar (SAR) receiver implemented in 130nm CMOS technology is presented in this paper. The baseband and the ADC are integrated on a single chip, occupying 1.6mm2 (I and Q branch) of active silicon area. The baseband is selectable between 50MHz and 160MHz bandwidth through switches and the voltage gain can be controlled between 22dB and 27dB. The ADC has selectable mode of 5, 6, 7 and 8 bits via control switches. The baseband and the ADC achieve measured spurious-free dynamic range more than 45dBc over the 160MHz band. The circuits, which use a 1.2V supply voltage, dissipates minimum power of 214mW with 50MHz baseband and 5 bit mode ADC, and maximum power of 344mW with 160MHz baseband and 8 bit mode ADC.

Single and two-stage OTAs for high-speed CMOS pipelined ADCs

This paper compares one- and two stage operational transconductance amplifiers (OTAs) to be used in an 8-bit high speed (440-MS/s) deep submicron CMOS (130nm) low voltage (1.2V) pipelined Analogue to Digital Converter (ADC) based on an 1.5-bit double sampling Multiplying Digital to Analogue Converter (MDAC). The main emphasis is put on the OTA DC-gain, gain-bandwidth (GBW), differential linear output range VOPP and power consumption. Most basic OTAs are compared through the calculations and simulations. In the potential topologies (regulated single stage or two stage), single stage OTA has a better phase response and a lower power consumption, whereas two stage OTA achieves larger linear range.

Class D CMOS power amplifier with on/off logic for a multilevel outphasing transmitter

In this paper, we present a class D power amplifier (PA) design in 28 nm CMOS for a multilevel outphasing transmitter. For increased output power, the design consists of eight unit PAs with cascoded output stages. In order to improve back-off efficiency from conventional outphasing, the PAs are switched on and off in pairs for different amplitude levels, which is challenging to implement with cascoded class D. As a solution, we introduce a new on/off switching method based on logic gates utilizing two square wave voltages to produce either a similar square wave or a constant voltage. This method enables a higher level of integration by using low-voltage digital signals for on/off control, while eliminating the timing mismatch between output transistors caused by a level shifter. The simulated peak output power of the PA is 32.4 dBm, and its peak efficiency is 34.1%.

Operational amplifier design for high-speed pipelined Analog-to-Digital Converters in deep-submicron CMOS processes

In this paper, design challenges of an operational amplifier (opamp) for medium-resolution pipelined Analog-to-Digital Converters (ADCs) in deep-submicron CMOS processes are discussed. Comparisons are made between basic opamp topologies in 130nm CMOS process, concerning particularly on gain, bandwidth, signal headroom and power consumption with 1.2V supply.

A 30-dBm Class-D Power Amplifier with On/Off Logic for an Integrated Tri-Phasing Transmitter in 28-nm CMOS

This paper presents an eight-unit class-D power amplifier (PA), implemented in 28-nm CMOS. The PA is designed to utilize tri-phasing modulation, which combines coarse-amplitude polar modulation with fine-resolution outphasing components. This new technique enables achieving the back-off efficiency of multilevel outphasing without linearity-degrading discontinuities in the output waveform. Each PA unit contains a cascoded output stage with a 3.6-V supply voltage, and on/off logic enabling multilevel operation controlled by low-voltage signals. The PA achieves a peak output power of 29.7 dBm with a 34.7% efficiency, and is verified to operate with aggregated LTE signals at bandwidths up to 60 MHz at 1.7-GHz carrier frequency.

13.5 A 0.35-to-2.6GHz multilevel outphasing transmitter with a digital interpolating phase modulator enabling up to 400MHz instantaneous bandwidth

Advanced wireless radio standards set stringent requirements on the bandwidth, frequency range and reconfigurability of base-station transmitters. Recently, the outphasing concept has shown promise of wide bandwidth while taking advantage of process scaling with extensive exploitation of rail-to-rail signaling. Recent outphasing transmitter designs have often focused on power-amplifier (PA) and power-combiner implementations while omitting the phase modulator [1,2]. Moreover, previously reported transmitters with integrated digital phase modulators have only shown bandwidths up to 40MHz [3,4], although 133MHz has been demonstrated at 10GHz carrier frequency utilizing phase modulators based on conventional IQ-DACs [5]. Thus, digital-intensive outphasing transmitters capable of modulation with hundreds of MHz bandwidth at existing cellular frequency bands have not yet been published. To address the aforementioned challenge, this paper introduces a multilevel outphasing transmitter with four amplitude levels, including the first prototype implementation based on the digital interpolating phase modulator concept [6]. The transmitter is targeted for 5G picocell base stations and has been verified to operate with instantaneous bandwidth up to 400MHz. In addition, the developed phase modulator eliminates the need for complex on-chip frequency synthesizers by introducing digital carrier frequency generation, demonstrated between 0.35 and 2.6GHz, while utilizing a single 1.8GHz reference clock.

Multilevel outphasing power amplifier system with a transmission-line power combiner

This paper presents a multilevel outphasing power amplifier (PA) system consisting of eight class-D unit PAs on 28 nm CMOS and an off-chip transmission-line power combiner. The combiner, implemented on PCB with microstrip lines, was designed to operate at 1.8 GHz frequency and filter out the third and fifth harmonics generated by the PAs. The combiner layout was designed so that the line spacing increases towards the output to reduce coupling, while the lines are equal in length. The simulated maximum output power is 32.3 dBm (1.71 W) with an efficiency of 34.4%. With 20 MHz and 100 MHz LTE signals, average efficiencies of 15.2% and 15.1% were achieved, respectively.

Multiband integrated synthetic aperture radar (SAR) receiver

An integrated receiver consisting of RF front ends, analog baseband chain with an analog to digital converter (ADC) for a Synthetic Aperture Radar (SAR) implemented in 130 nm CMOS technology is presented in this paper. The circuits are integrated on a single chip with a size of 10.88 mm2. The RF front end consists of three parallel signal channels intended for L,C and X-band of the SAR receiver. The baseband (BB) is selectable between 50 MHz and 160 MHz bandwidths through switches. The ADC has selectable mode of 5, 6, 7 and 8 bits via control switches. The receiver has a nominal gain of 40 dB and 37 dB and noise figure of 11 dB and 13.5 dB for 160 MHz BB filter at room temperature for L-band and C-band, respectively. The circuits, which use a 1.2 V supply voltage, dissipate maximum power of 650 mW with 50 MHz baseband and 8 bit mode ADC, and maximum power of 800 mW with 160 MHz baseband and 8 bit mode ADC.