Ville Saari

Wideband 2 to 6GHz RF front-end with blocker filtering

This paper presents a wideband blocker filtering technique for a RF front-end. The wideband LNA and the transferred impedance filter are implemented as part of a receiver to demonstrate the feasibility of the system. The front-end achieves a gain of 43 and 41 dB, noise figure of 3.2 and 5.7 dB with IIP3 of −13 and −5 dBm with the transferred-impedance filter turned off and on, respectively. Added selectivity of 6 dB is achieved by using the structure described in this paper.

A 0.7 – 2.6 GHz high-linearity rf front-end for cognitive radio spectrum sensing

A wideband receiver for cognitive radio spectrum sensing unit is presented. The circuit consists of a high-linearity low-noise amplifier, passive mixer, and base-band buffer. IQ signals for the LO are generated using a divide-by-two circuit. Low-noise amplifier includes common-gate common-source combination for simultaneous interference suppression and noise canceling. The receiver operates in the LTE bands at 0.7 – 2.6 GHz, with measured performance of 31-dB gain, 11-dB noise figure, and 2-dBm IIP3 linearity. The circuit is fabricated in 65-nm CMOS technology and it occupies 0.3-mm2 active area.

Analog baseband chain with analog to digital converter (ADC) of Synthetic Aperture Radar (SAR) receiver

An analog baseband chain together with an analog to digital converter (ADC) for a Synthetic Aperture Radar (SAR) receiver implemented in 130nm CMOS technology is presented in this paper. The baseband and the ADC are integrated on a single chip, occupying 1.6mm2 (I and Q branch) of active silicon area. The baseband is selectable between 50MHz and 160MHz bandwidth through switches and the voltage gain can be controlled between 22dB and 27dB. The ADC has selectable mode of 5, 6, 7 and 8 bits via control switches. The baseband and the ADC achieve measured spurious-free dynamic range more than 45dBc over the 160MHz band. The circuits, which use a 1.2V supply voltage, dissipates minimum power of 214mW with 50MHz baseband and 5 bit mode ADC, and maximum power of 344mW with 160MHz baseband and 8 bit mode ADC.

A 190MHz 4nV/√Hz analog baseband chain of Synthetic Aperture Radar (SAR) receiver

An analog baseband chain for a Synthetic Aperture Radar (SAR) receiver implemented in a 130nm CMOS technology is presented in this paper. Occupying 0.23mm2 of silicon area, the baseband chain consists of a three-stage Variable Gain Amplifier (VGA), a 5th-order gm-C Low Pass Filter (LPF) and an Output Buffer (OBUF). The gain of the chain can be controlled by tuning the control voltages of the VGA and has a range from 25dB to 34dB. In addition, the LPF has an 8dB gain to meet the required dynamic range of the following block. The bandwidth of the LPF is programmable from 120MHz to 190MHz by means of capacitor matrices. The chain, which uses a 1.2V supply voltage, achieves 4nV/√Hz of input-referred noise density and −42dBV in-band IIP3.

A 9-bit current-steering Digital to Analog Converter for differential dc-offset compensation of a baseband chain

A current-steering Digital to Analog Converter (IDAC) to compensate dc-offset of a baseband chain in a Synthetic Aperture Radar (SAR) receiver is presented in this paper. The differential dc-offset can be injected with the current steer controlled by 9 digital control bits. The simulated LSB is 1.4 mV and the differential voltage range is 283 mV when it is connected to the baseband chain. This IDAC is implemented in a 130 nm CMOS technology and occupies 0.05 mm2 of silicon area. From the postlayout simulation of the IDAC, the voltage range satisfies the specification obtained from the Monte Carlo simulations of the baseband chain. The 1 Least Significant Bit (1LSB) of the IDAC ensure the dc-offset at the input of the following ADC met the system requirement.

Multiband integrated synthetic aperture radar (SAR) receiver

An integrated receiver consisting of RF front ends, analog baseband chain with an analog to digital converter (ADC) for a Synthetic Aperture Radar (SAR) implemented in 130 nm CMOS technology is presented in this paper. The circuits are integrated on a single chip with a size of 10.88 mm2. The RF front end consists of three parallel signal channels intended for L,C and X-band of the SAR receiver. The baseband (BB) is selectable between 50 MHz and 160 MHz bandwidths through switches. The ADC has selectable mode of 5, 6, 7 and 8 bits via control switches. The receiver has a nominal gain of 40 dB and 37 dB and noise figure of 11 dB and 13.5 dB for 160 MHz BB filter at room temperature for L-band and C-band, respectively. The circuits, which use a 1.2 V supply voltage, dissipate maximum power of 650 mW with 50 MHz baseband and 8 bit mode ADC, and maximum power of 800 mW with 160 MHz baseband and 8 bit mode ADC.