Markondeya Raj Pulugurtha

Multichip Embedding Technology Using Fine-Pitch Cu–Cu Interconnections

Increasing performance and functional density while maintaining low cost is a catalyst for technological progress in the field of packaging. From flip-chip with solder to a hybrid approach of copper and solder, many methods have been created to reach this objective. The 3-D Packaging Research Center at Georgia Tech has been revolutionizing interconnection technology with the multichip embedding chip-last approach, which utilizes ultrathin adhesive-bonded copper bumps to enable ultrafine-pitch chip-to-package interconnections. This technology has been proven to be highly reliable using a low-cost low-temperature direct copper-to-copper bonding approach at 30-μm pitch and ~20-μm standoff height copper-to-copper interconnections. This interconnection method provides a platform for integration with flip-chip packages through its proven ability to work well with different die sizes and thicknesses bonded to the surface of ultrathin organic substrates. The next step in advancing the chip-last approach is to investigate chip embedding at the single-chip and multichip levels. Consequently, this paper focuses on: 1) the design and fabrication of the test vehicle to examine the reliability of the previously demonstrated copper-to-copper interconnections after embedding a thin die in an organic substrate, and 2) assembly process development and reliability data for the interconnections. Specifically, advances in the assembly process include: 1) a novel method to perform chip-last assembly at the panel level leading to a 10-15 times reduction in assembly time per die, and 2) an improved two-step assembly process to achieve simultaneous die embedding and cavity planarization. This embedding technology and its advancements not only allow actives to be embedded in organic substrates but also enables higher functional integration at high-throughput, making chip-last adhesive bonding with low-profile copper-to-copper interconnections a robust chip embedding solution for the next generation of highly integrated heterogeneous subsystems.

Interconnection materials, processes and tools for fine-pitch panel assembly of ultra-thin glass substrates

The needs for higher speed and bandwidth at low power for portable and high-performance applications has been driving recent innovations in packaging technologies with new substrate platforms with finer lithographic capability and dimensional stability, such as ultra-thin glass, to enable off-chip interconnections pitch scaling, down to 30μm. Copper pillar flip-chip thermocompression bonding (TCB) has subsequently become a pervasive technology in the past decade, and is now considered as the next interconnection and assembly node for smart mobile and high-performance systems. However, additional innovations are needed to achieve high-throughput thermocompression bonding on fragile and thin glass, with short cycle times and process conditions within HVM (high-volume manufacturing) tool capability. These include material advances in surface finishes and pre-applied underfill materials with built-in flux, along with a unique co-development strategy to provide high-speed solutions with optimized TCB profiles that consider the dynamic thermal behavior of high-density glass substrates, underfill curing kinetics, as well as tool compatibility. These innovations are the key focus of this paper. Finite element heat transfer and thermomechanical modeling were carried out to emulate assembly processes and compare the behavior of glass substrates to that of current technologies. Residual stresses created during the cool-down phase were extracted to help define process windows for stress management in interconnections, by fine control of intermetallics (IMC) formation. Emerging surface finish chemistries compatible with high-density wiring with sub-10μm spacings, such as OSP or EPAG (electroless Pd, autocatalytic Au) finish, were also evaluated for their effect on the formed IMC systems. A new set of no-flow snap-cure underfill materials with high thermal stability, beyond existing conductive films or pastes, was developed in synergy with tools and processes for compatibility with advanced substrate technologies. Model predictions were validated with assembly trials on ultra-thin glass and organic substrates with 100μm thin cores. Design guidelines for bonding tools, materials and processes were finally derived, for high-speed thermocompression bonding, customized to the performance, reliability and cost needs of next-generation mobile and high-performance systems.

Modeling, design and demonstration of integrated electromagnetic shielding for miniaturized RF SOP glass packages

This paper demonstrates, for the first time, an integrated trench-based shielding for electromagnetic interference (EMI) isolation between components in an ultra-miniaturized radio frequency (RF) package. A novel component-level shielding structure is explored and developed using metallized trenches formed in the build-up layers of ultra-thin glass substrates. Through full-wave electromagnetic (EM) simulation, the coupling between different passive structures are compared. Additionally, the shielding effectiveness of trench-based structures are compared with traditional via-based shields. Further, the shield effectiveness of different magnetic and non-magnetic shield materials are compared through analytical modeling. Based on these modeling results, a representative shield structure is designed, fabricated and characterized to correlate its performance with simulations. It is observed through measurements, that package-integrated trench-based shields provide up to 25dB more lateral isolation than via-arrays.

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High-k barium strontium titanate (BST) thin films were deposited onto glass substrates to demonstrate integrated capacitors for power supply in high-speed digital packages. Ferroelectric BST films were sputter deposited onto solution-derived lanthanum nickel oxide (LNO) electrodes. Zirconium oxide was studied for the first time as a barrier between glass and LNO electrodes to prevent electrode (LNO) interdiffusion into the glass substrate. The LNO and BST films were annealed in an oxygen-rich atmosphere at 650°C. A capacitance density of 20-30 nF/mm2 was obtained at an operating voltage of 3 V. Leakage currents of 1-10 nA/nF were measured up to 3 V. These properties demonstrate the potential for low-cost high-k thin-film decoupling capacitors in 2-D, 2.5-D, and 3-D glass interposers. A process to integrate and test such capacitors on glass substrates using sequential dielectric and electrode patterning is also demonstrated.

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This paper demonstrates, for the first time, 3D integrated passive device (IPD) diplexers on ultra-thin glass substrates for wireless local area network (WLAN) application in mobile devices. The designed LC-based diplexer was composed of a low-band filter and a high-band filter, built on ultra-thin glass substrates. The two filters were designed on each side of the glass substrate and interconnected by through-package-vias (TPVs) to form a 3D IPD. Ultra-thin and low-loss dryfilm dielectrics were utilized for improved electrical performance as well as to achieve high-density of passives integration. The demonstrated 3D IPD diplexer is 3-4X thinner than current LTCC devices, with lateral dimensions of 1.1mm x 1.3mm in a thickness of 200μm resulting in a low insertion loss of less than 1dB for pass bands and more than 24dB stop-band rejection.

Thin-Film Capacitors With Conducting Oxide Electrodes on Glass Substrates for Power-Supply Applications

This paper describes ultrathin tantalum-based high volumetric-density power capacitors with low leakage properties for 1-10-MHz frequency applications. Nano dielectrics with low-defect density were grown on nanoporous tantalum anodes using the self-limiting anodization process. The fundamental mechanisms that govern the film growth and quality were investigated to provide anodization process guidelines. Conducting polymer nanoparticles were used as the cathodes. Complete filling of conducting polymer was achieved by the optimization of conducting polymer application process. Energy dispersive spectroscopy and structural SEM studies were performed to investigate the morphology and structure of the tantalum pentoxide films. The fabricated capacitor showed 0.6-0.8 μF/mm2 of capacitance density in the 1-10-MHz range, in substrate compatible ultrathin (<;75 μm) form factors. This is the highest volumetric density reported for such thin-film capacitors in a megahertz frequency range.

Design and Demonstration of Ultra-Thin Glass 3D IPD Diplexers

This paper addresses the thermal dissipation of power amplifier (PA) chips, which is one of the biggest challenges in the development of ultra-miniaturized glass-based RF modules. Glass packages with 3D or double-side active and passive integration offer the best miniaturization and performance enhancement for RF modules because glass has ultra-low loss, dimensional stability for precision thinfilm components, ability to process through-vias in large panels to reduce cost. However, glass is a poor thermal conductor. Cooling of the high-power PA die with integrated miniaturized RF modules is, therefore, a key challenge. This paper provides extensive modeling studies of RF power amplifier modules with copper thermal vias in ultra-miniaturized glass, without additional process steps. It considers various power amplifier design options such as: Si vs. Silicon-on-Insulator (SOI); location of die hotspot; via geometry; and conformal vs. fully-filled vias, and provides optimal design recommendations with modeling and analysis.

Ultrathin, Substrate-Integrated, and Self-Healing Nanocapacitors With Low-Leakage Currents and High-Operating Frequencies

Thin integrated passive devices (IPDs) will play a critical role in the miniaturization of future high-performance electronic and bioelectronic systems. Silicon-based capacitors are currently manufactured with expensive processes such as sputtering and atomic layer deposition. Solution-deposited electrodes and dielectrics in trench and through-via structures provide alternative low-cost routes. Two solution-deposition techniques, spin-coating and vacuum infiltration, are investigated in this paper. A representative all-solution-derived thin-film capacitor consisting of sol-gel lanthanum nickel oxide (LNO) as the electrode, and sol-gel lead zirconate titanate as the dielectric thin-film is demonstrated in the first part of this paper. The role of barriers in reducing leakage currents is studied using three electrode systems: LNO/Si, LNO/ZrO2/Si, and LNO/Pt/Ta/Si. Capacitors with LNO electrodes directly deposited on naturally oxidized silicon resulted in higher leakages, more defects and a lower yield. The results show that the zirconia barrier suppresses the leakage current in the dielectric. The second part of this paper describes sol-gel films deposited in the through-via and trench surfaces to demonstrate the sol-gel conformal coating technique. Scanning electron microscopy cross-section analysis shows that the vacuum infiltration conformally coated through-vias. These solution deposition techniques may have the potential to fabricate IPD capacitors at low cost.

Modeling, design and demonstration of ultra-miniaturized glass PA modules with efficient thermal dissipation

This paper introduces an innovative concept of electrical-thermal co-design for high-Q 3D inductors using through-package-via (TPV)-based copper networks in ultra-thin power amplifier-integrated glass modules. The copper networks are designed to provide high quality factor inductors, and also simultaneously enable heat transfer in ultra-miniaturized glass packages. Such TPV-based 3D inductors achieved the highest Q factor (>150 @ 1 GHz, >200 @ 2.4 GHz, SRF > 25 GHz), 7 times greater than that of the state-of-the-art package embedded inductors at LTE frequencies. The thermal structure, with power amplifier die assembled onto it, also reduces the package size by placing the embedded TPV-based inductor adjacent to it without affecting its Q.

All-Solution Thin-film Capacitors and Their Deposition in Trench and Through-Via Structures

This paper demonstrates, for the first time, an integrated radio frequency (RF) front-end module (FEM) with precision matching circuits in ultra-miniaturized glass substrates for LTE applications. Through full-wave electromagnetic (EM) simulations, electrical performance of these glass-based long term evolution (LTE) packages is compared with traditional RF modules with surface mount devices (SMDs), and organic laminates with embedded passives and actives. RF front-end modules with 3D or double-side thin film passive components on glass-based substrates are fabricated and characterized to correlate their performance with EM simulations.