Markus Forsberg

Effect of dopants on chemical mechanical polishing of Silicon

In microelectronic manufacturing, chemical mechanical polishing (CMP) of silicon is becoming a more and more important process. This work investigates the effect of dopants on CMP of silicon. A high boron concentration is found to reduce the removal rate. The boron induced reduction is clearly demonstrated by observing boron diffused areas on a wafer protrude during polishing. A high phosphorus concentration enhances the removal rate. It is also found that the removal rate is lower for the Si(111) compared to the Si(100) orientation.

Geometrically Defined All-Diamond Abrasive Surfaces for Pad Conditioning in Chemical Mechanical Polishing

Geometrically Defined All-Diamond Abrasive Surfaces for Pad Conditioning in Chemical Mechanical Polishing

A Geometrically Defined All-Diamond Pad Conditioner

This work presents a geometrically defined pad conditioner fabricated by anisotropic etching of silicon to produce a well-defined mold and subsequently CVD diamond layer is deposited on this mold. Finally, the silicon wafer is etched away, exhibiting the all-diamond tool surface. The new type of pad conditioner offers very sharp pyramidal tips, all equal in size. The excellent sharpness leads to high roughening capability while keeping the pad removal low. The precise tip position and height results in a unique uniformity of scratches produced, hence offering a new level of process control.Copyright

A Shallow and Deep Trench Isolation Process Module for RF BiCMOS

Chemical mechanical polishing (CMP) has been used for a long time in the manufacturing of prime silicon wafers for the IC industry. Lately, other substrates, such as silicon-on-insulator has become in use which requires a greater control of the silicon CMP process. CMP is used to planarize oxide interlevel dielectric and to remove excessive tungsten after plug filling in the Al interconnection technology. In Cu interconnection technology, the plugs and wiring are filled in one step and excessive Cu is removed by CMP. In front end processing, CMP is used to realize shallow trench isolation (STI), to planarize trench capacitors in dynamic random access memories (DRAM) and in novel gate concepts. This thesis is focused on CMP for front end processing, which is the processing on the device level and the starting material. The effects of dopants, crystal orientation and process parameters on silicon removal rate are investigated. CMP and silicon wafer bonding is investigated. Also, plasma assisted wafer bonding to form InP MOS structures is investigated. A complexity of using STI in bipolar and BiCMOS processes is the integration of STI with deep trench isolation (DTI). A process module to realize STI/DTI, which introduces a poly CMP step to planarize the deep trench filling, is presented. Another investigated front end application is to remove the overgrowth in selectively epitaxially grown collector for a SiGe heterojunction bipolar transistor. CMP is also investigated for rounding, which could be beneficial for stress reduction or to create microoptical devices, using a pad softer than pads used for planarization. An issue in CMP for planarization is glazing of the pad, which results in a decrease in removal rate. To retain a stable removal rate, the pad needs to be conditioned. This thesis introduces a geometrically defined abrasive surface for pad conditioning.