Sven Beyer
GlobalFoundries
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Publication
Featured researches published by Sven Beyer.
international conference on ultimate integration on silicon | 2013
Jan Hoentschel; Shiang Yang Ong; Torben Balzer; Nicolas Sassiat; Ran Yan; Tom Herrmann; Stefan Flachowsky; Carsten Grass; Sven Beyer; Oliver Kallensee; Yu-Yin Lin; Adelina Shickova; Armin Muehlhoff; Claudia Kretzschmar; Joerg Winkler; Maciej Wiatr; Manfred Horstmann
Different gate stack optimizations and substrate dependent strain interactions have been studied and implemented in a cost-effective 28nm VLSI ultra low power technology. Drive current improvements for NFET I<sub>D,SAT</sub> = 870μA/μm and PFET I<sub>D,SAT</sub> = 465μA/μm at I<sub>OFF</sub> = 1nA/μm and V<sub>DS</sub> = 1V can be demonstrated by using compressive and tensile contact layers on (100)/<;110> substrates. Work function optimizations result in a proper threshold voltage adjustment and improved reliability behavior for 28nm ultra low power technologies. SOC level test design implementations show consistent yield as well as improved performance.
Archive | 2006
Thorsten Kammler; Patrick Press; Rolf Stephan; Sven Beyer
Archive | 2010
Sven Beyer; Markus Lenski; Richard Carter; Klaus Hempel
Archive | 2010
Jan Hoentschel; Sven Beyer; Thilo Scheiper; Uwe Griebenow
Archive | 2010
Richard Carter; Falk Graetsch; Martin Trentzsch; Sven Beyer; Berthold Reimer; Robert Binder; Boris Bayha
Archive | 2009
Sven Beyer; Patrick Press; Rainer Giedigkeit; Jan Hoentschel
Archive | 2010
Richard Carter; Martin Trentzsch; Sven Beyer; Rohit Pal
Archive | 2013
Uwe Griebenow; Jan Hoentschel; Thilo Scheiper; Sven Beyer
Archive | 2010
Jan Hoentschel; Sven Beyer; Uwe Griebenow
Archive | 2010
Richard Carter; Sven Beyer; Joachim Metzger; Robert Binder
