Martin Kovac

An approach towards selection of the oscillation frequency for oscillation test of analog ICs

The paper deals with a new approach to selection of the optimum value of the oscillation frequency towards increasing the efficiency of the oscillation-based test methods in covering hard-detectable short faults in nanoscale technologies. For this purpose, the Describing-Function analysis was used to calculate of the oscillation frequency of a simple oscillator (an analog circuit under test) modeled in MATLAB. Accuracy of the model was evaluated through comparison of computed parameters to parameters achieved for the same circuit in Cadence.

130 nm CMOS Bulk-Driven Variable Gain Amplifier for Low-Voltage Applications

In this paper, a variable gain amplifier (VGA) designed in 130 nm CMOS technology is presented. The proposed amplifier is based on the bulk-driven (BD) design approach, which brings a possibility t...

Low-voltage bulk-driven variable gain amplifier in 130 nm CMOS technology

In this paper, a variable gain amplifier designed in 130 nm CMOS technology is presented. The proposed amplifier is based on the bulk-driven approach, which brings a possibility to operate with low supply voltage (i.e. 0.6 V). Since the supply voltage of only 0.6 V is used for the amplifier to operate, there is no latchup risk that usually represents the main drawback of the bulk-driven approach. As an input stage, bulk driven transistors are used, which makes possible to operate in the rail-to-rail input voltage range. Achieved simulation results indicate that gain of the proposed VGA can be varied in a wide range, which together with the low supply voltage feature make the proposed amplifier useful for low-voltage and low-power applications.

Ultra-low-voltage driver for large load capacitance in 130nm CMOS technology

This paper presents design of the inverter-based driver for low-voltage applications, with topology for boosting the transistors overdrive voltage. The proposed driver topology was designed through detailed circuit analysis and optimization, and it is suitable for use in a switched capacitor charge pump. The driver was designed in 130 nm CMOS technology and verified by simulations including technology corners. Core of the proposed driver — the inverter uses power supply voltage of 200 mV. The whole boosted driver achieves a propagation delay of 9.2 ns and energy consumption of 92.12 µW for the value of load capacitor is 100 pF. Due to the low-power consumption, the proposed driver was satisfactory used in a self-powered charge pump systems.

Variable-gain amplifier for ultra-low voltage applications in 130nm CMOS technology

The paper deals with design and analysis of a variable-gain amplifier (VGA) working with a very low supply voltage, which is targeted for low-power applications. The proposed amplifier was designed using the bulk-driven approach, which is suitable for ultra-low voltage circuits. Since the power supply voltage is less than 0.6 V, there is no risk of latchup that is usually the main drawback of bulk-driven topologies. The proposed VGA was designed in 130 nm CMOS technology with the supply voltage of 0.4 V. The achieved results indicate that gain of the designed VGA can be varied from 0 dB to 18 dB. Therefore, it can be effectively used in the many applications such as automatic gain control loop with ultra-low value of supply voltage, where the dynamic range is the important parameter.

Ultra-low-voltage boosted driver for self-powered systems

Abstract This paper deals with the ultra low-voltage design and application of an inverter-based driver. In order to ensure a reliable value of the overdrive voltage for transistors, the topology based on a boosting technique was used. The driver was designed in 130 nm CMOS technology and verified by simulations including technology corners and measurement of prototyped chips. The whole boosted driver achieves energy consumption of 92.12 μW for the load capacitor of 100 pF. Due to the low-power consumption and promising measured propagation delay, the designed driver was successfully implemented in a self-powered dynamic threshold charge pump. To ensure the reliable start-up, the minimum precharging voltage of the output capacitor has been investigated. The start–up conditions and achieved parameters were verified by measurement and compared to other related works. The optimum point for reliable start of the charge pump has been observed for the clock frequency of about 160 kHz, where the minimum start-up voltage of 126 mV is needed. In such a case, the start-up time is 1.05 ms and the output voltage of 379 mV will be reached.

Digital methods of calibration for analog integrated circuits in nanotechnologies

This work deals with the influence of increasing rate of integration (i.e. technology downscale) on the main parameters of integrated circuits. Our concerns are focused on calibration methods of analog integrated circuits that can compensate undesired side effects of technology downscale. The paper describes both the general principle of calibration system as well as design requirements for main blocks of the calibration subcircuit. Then, the approach for calibration employment in operational amplifiers is described, where the voltage offset cancellation is of the main concern. Consequently, a specific application of previously described calibration fundamentals is presented. For this purpose, statistical results on the input offset voltage of the operational amplifier are used, where the operational amplifier is realized in 130 nm CMOS technology.

Low-power bulk-driven rail-to-rail comparator in 130 nm CMOS technology

This paper addresses a design and performance evaluation of a non-clocked comparator circuit intended to work in a wide temperature range with very low value of the power supply voltage. Due to low voltage swing, the input voltage range is set to be rail-to-rail. The target fabrication process is a standard twin-well 130 nm CMOS technology, with appropriate parameters required to meet circuit specifications. The nominal power supply voltage for this technology has been halved to the value of 0.6 V. However, the proposed circuit topology is able to work with even lower supply voltage. The comparator was designed employing gm/ID methodology along with bulk-driven transistors. The post-layout simulations have been carried out in order to evaluate the circuit performance in all process and temperature corners as well as by means of Monte-Carlo analysis. Very promising results have been obtained and the proposed comparator was successfully employed in a charge pump system.

Investigation of on-chip coil in 130 nm standard CMOS for WPT and bio-applications

The wireless power transfer (WPT) systems, in conjunction with active implantable medical devices (AIMDs), belong to the most discussed topics in last years. Recently, the low frequency (inductive) or near-field electromagnetic energy transfer make the integration of AIMDs easier and simplified that supports their miniaturization. This paper deals with the possibilities of realization of the secondary coil directly on integrated circuit (IC) chip in standard UMC 130 nm CMOS process. We also bring a comparison of the proposed solution to the most related work. At this stage, the verification was done by simulation. Designed symmetrical multilayer stacked inductor achieves the maximum quality factor of 6.24 at 224.1 MHz, 51.33 nH inductance at the maximum quality factor, the maximum inductance of 224.73 nH, and self-resonance frequency (SFR) of 462 MHz. The paper also brings discussion about how the presence of biocompatible or biostable dielectric isolators (with low and high relative permittivity) influences the inductor parameters and performance.

Towards automatic gain control low-power amplifier in 130 nm CMOS technology

The paper addresses the design of a bulk-driven variable gain amplifier (VGA) in 130 nm general purpose CMOS technology. The VGA is intended to be employed within a low-power automatic gain control (AGC) block, which requires an examination of possible gain setting approaches. The mentioned investigation as well as the evaluation and comparison of the obtained results are presented. The amplifier has been designed to work with the power supply voltage of only 0.6 V, which introduces a whole series of challenges and obstacles. However, it also eliminates one of the main problems associated with bulk-driven circuits - the latch-up effect.