Daniele Giaffreda

Local Shunting in Multicrystalline Silicon Solar Cells: Distributed Electrical Simulations and Experiments

In this paper, we analyze the effect of local shunts in photovoltaic (PV) solar cells by experimental characterization and distributed electrical simulations. To this purpose, we developed a quasi-3-D distributed electrical network that is based on two-diode circuit elementary units. It allows accounting for resistive losses associated to the transport through the emitter, the fingers and the busbars, and to local defects in the semiconductor. The electrical parameters of the equivalent circuit units are calibrated according to experiments performed on multicrystalline (mc-Si) silicon solar cells, including samples that feature local shunts due to localized defects, which lead to nonuniform distribution of electrical and optical properties. The distributed electrical simulations account for the degradation of fill factor and power conversion efficiency in case of local shunting. Moreover, by combining the proposed tool with a RC thermal network it is possible to estimate the temperature distribution in a shunted solar cell. Our analysis shows how a shunted cell that operates under hot-spot conditions is subject to significant local overheating, which possibly lead to permanent PV cell damages.

Effect of shunt resistance on the performance of mc-Silicon solar cells: a combined electro-optical and thermal investigation

In this paper we discuss the effect of shunt resistance on the electro-optical characteristics of multicrystalline silicon (mc-Si) solar cells at different illumination levels. The analysis is based on combined electro-optical characterization and thermographic measurements of solar cells with similar efficiencies, but with different shunt resistance levels. In order to understand how the shunt resistance can affect the performance of mc-Si solar cells, a special setup for J-V characterization at several illumination levels was developed. Results indicate that (i) a low shunt resistance is strongly correlated to the presence of hot spots, which can be identified by means of infrared thermography; (ii) solar cells with different shunt resistance levels can show significantly different fill factors and efficiencies, particularly at low irradiation levels. This can strongly influence the reliability of modules at low illumination conditions; (iii) the electrical characteristics of mc-Si solar cells can be modeled with good results, by considering the equivalent two-diode electrical model and solving it by a circuit simulator like SPICE.

Modeling and Detection of Hotspot in Shaded Photovoltaic Cells

In this paper, we address the problem of modeling the thermal behavior of photovoltaic (PV) cells undergoing a hotspot condition. In case of shading, PV cells may experience a dramatic temperature increase, with consequent reduction of the provided power. Our model has been validated against experimental data, and has highlighted a counterintuitive PV cell behavior, that should be considered to improve the energy efficiency of PV arrays. Then, we propose a hotspot detection scheme, enabling to identify the PV module that is under hotspot condition. Such a scheme can be used to avoid the permanent damage of the cells under hotspot, thus their drawback on the power efficiency of the entire PV system.

Model for Thermal Behavior of Shaded Photovoltaic Cells under Hot-Spot Condition

We address the problem of modeling the thermal behavior of photovoltaic (PV) cells that, due to their being exposed to shading, may experience a dramatic temperature increase (a phenomenon referred to as hot-spot) with consequent reduction of the provided power. Our proposed model has been validated against experimental data, and constitutes a first preliminary step towards the development of shading-tolerant approaches, while also highlighting a counterintuitive PV cell behavior useful to energy efficient PC array design.

Understanding the Influence of Busbars in Large-Area IBC Solar Cells by Distributed SPICE Simulations

In this paper, we model a large-area high-efficiency interdigitated back-contact (IBC) solar cell by means of a distributed electrical network. The simulation tool allows accounting for the distributed resistive effects in diffusions and metallization. The model also considers the electrical shading effect and resistive losses due to both back-surface field (BSF) and emitter busbars. A calibrated model is used to investigate the case of a large-area (15.6 × 15.6 cm2) IBC cell, in which we investigate the influence of key busbar parameters: number of busbars, busbar width, soldering pitch (for module connection), and metal sheet resistance. The predictive simulations allow finding out the optimum number of busbars, arising from a tradeoff between the electrical shading effect due to the BSF busbars and resistive losses due to the emitter busbars and the fingers. Moreover, we show how the distance between soldering points on the metal busbars influences the choice of the busbar width. We found out that if an adequate number (>7) of soldering points is adopted, the busbar width should be kept lower than 0.5 mm. On the other hand, the adoption of a thick Cu-plating (15 μm) leads to an increase of efficiency of 0.2%abs with respect to the case of sputtered Al metal (3 μm thick).

Secure communication protocol for wireless sensor networks

We propose a new communication protocol for wireless sensor networks, allowing to make them secure with respect to malicious attacks. Compared to standard secure protocols (e.g., the IEEE 802.15.4 and the ZigBee), the one we propose allows to increase security significantly, at negligible impact on node complexity. A possible hardware scheme to implement our protocol is also proposed.

On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter

We present a novel low cost scheme for the on-die measurement of either clock jitter, or process parameter variations. By re-using and properly modifying the Ring Oscillators (ROs) that are currently widely employed for process parameter variation measurement in high performance microprocessors, our proposed scheme can be easily set in either the process parameter variation measurement mode, or the clock jitter measurement mode, by acting on an external control signal. This way, during the test or debug phase, clock jitter can also be measured at negligible area and power costs with respect to process parameter variation measurement only. Our scheme is scalable in the provided clock jitter measurement resolution, while allowing the same process parameter variation measurement resolution as the currently employed RO based schemes. Moreover, due to its allowing both process parameter variation and clock jitter measurements, our scheme features accurate clock jitter measurement despite the possible presence of significant process parameter variations.

Low-Cost On-Chip Clock Jitter Measurement Scheme

In this paper, we present a low-cost, on-chip clock jitter digital measurement scheme for high performance microprocessors. It enables in situ jitter measurement during the test or debug phase. It provides very high measurement resolution and accuracy, despite the possible presence of power supply noise (representing a major source of clock jitter), at low area and power costs. The achieved resolution is scalable with technology node and can in principle be increased as much as desired, at low additional costs in terms of area overhead and power consumption. We show that, for the case of high performance microprocessors employing ring oscillators (ROs) to measure process parameter variations (PPVs), our jitter measurement scheme can be implemented by reusing part of such ROs, thus allowing to measure clock jitter with a very limited cost increase compared with PPV measurement only, and with no impact on parameter variation measurement resolution.

Faults Affecting Energy-Harvesting Circuits of Self-Powered Wireless Sensors and Their Possible Concurrent Detection

We analyze the effects of faults on an energy-harvesting circuit (EHC) providing power to a wireless biomedical multisensor node. We show that such faults may prevent the EHC from producing the power supply voltage level required by the multisensor node. Then, we propose a low-cost (in terms of power consumption and area overhead) additional circuit monitoring the voltage level produced by the EHC continuously, and concurrently with the normal operation of the device. Such a monitor gives an error indication if the generated voltage falls below the minimum value required by the sensor node to operate correctly, thus allowing the activation of proper recovery actions to guarantee system fault tolerance. The proposed monitor is self-checking with regard to the internal faults that can occur during its in-field operation, thus providing an error signal when affected by faults itself.