Martin Rodgers

STLM: A Sidewall TLM Structure for Accurate Extraction of Ultralow Specific Contact Resistivity

We propose a very large scale integration compatible, modified transfer length method (TLM) structure, called sidewall TLM, to minimize the effect of spreading resistance and thus improving the resolution of the TLM method. This is achieved by allowing uniform current collection perpendicularly through the sidewall of the contact. We demonstrate statistically significant specific contact resistivity (ρ_c) extraction of 2×10^-8Ω cm² and 5×10^-9Ω cm² for n-type and p-type NiSi contacts, respectively, on a 300-mm wafer, which are about 50% less than those extracted using the conventional TLM structure. The proposed structure also shows a tighter distribution in the extracted ρ_c values. The results show the importance of such test structures to accurately extract ultralow ρ_c values relevant to sub-14-nm technology nodes.

FinFET parasitic resistance reduction by segregating shallow Sb, Ge and As implants at the silicide interface

This paper reports a new contact technology comprising antimony (Sb) co-implantation and segregation to reduce Schottky barrier height (SBH) and parasitic series resistance for N-FinFETs. Experiments with shallow Sb, Ge and As co-implantation in the source/drain (S/D) regions of SOI FinFET found that all three implant species significantly reduced extrinsic resistance. The Sb implant with a 5e13 cm-2 dose produced the best result with a 31% reduction of extrinsic resistance and a corresponding Ion increase of 19%. This optimum Sb implant is shown to reduce specific contact resistivity (ρc) below 10-8Ω-cm2 by decreasing the SBH and increasing the barrier steepness. Electrostatic control comparable to the reference device indicates no degradation in short channel effects for either Sb, Ge or As. This low ρc is promising to address key FinFET scaling issues associated with parasitic series resistance for the 14nm node and beyond.

Intrinsic Tolerance to Total Ionizing Dose Radiation in Gate-All-Around MOSFETs

We measured the total ionizing dose response of gate-all-around silicon nanowire n- and pMOSFETs to x-ray doses up to 2Mrad(SiO2). We show that they are radiation hard, with no degradation in threshold voltage, off-state current, or subthreshold slope, even at the highest dose for a wide range of bias conditions. We attribute this to the intrinsically rad-hard feature of the gate-all-around device design, where the channel is no longer in contact with any insulating layers that could form a parasitic channel.

Contact resistance improvement by dielectric breakdown in semiconductor-dielectric-metal contact

We propose an approach for reduction of the contact resistance by inducing dielectric breakdown in a Si-dielectric-metal contact stack. We observe a 36% reduction in the contact resistance as well as an improvement in the uniformity in the distribution after dielectric breakdown. The results open up interesting device applications in complementary metal oxide semiconductor technology.

Study of millisecond laser annealing on recrystallization, activation, and mobility of laser annealed SOI doped via arsenic ion implantation

Millisecond anneal techniques have been demonstrated to achieve fully recrystallized, highly activated, shallow, and abrupt junctions in silicon with both p- and n-type dopants due to the techniques fast time scale and high temperature. To understand and model the effects of millisecond laser annealing, knowledge of the true thermal profile experienced by the active semiconductor region must be known. This work simulates the impacts of a scanning laser in a series of shallow implants, and compares those results to experimental results. Arsenic ion (As+) implant energies of 10, 19, and 25 keV at doses of 1.5 × 1015 and 3 × 1015 cm−2 into a silicon-on-insulator substrate are studied to achieve different doping levels and amorphization depths. The recrystallization, activation, and mobility of the laser annealed, ion implanted experimental cells are then analyzed. For each experiment, Sentaurus technology computer aided design is used to create a calibrated 2D laser model to approximate the thermal budget of the lasing recipes (850–1250 °C) then using that output as an input into lattice kinetic Monte Carlo (LKMC) to simulate the solid phase epitaxial regrowth (SPER) during anneal of the various implant conditions. Sheet resistance and Hall effect measurements were used to correlate dopant activation and mobility with the regrowth process during laser anneal, showing the onset of high conductivity associated with completion of SPER in the films. The LKMC model shows an excellent agreement with cross section transmission electron microscopy, correlating the increase of conductivity with completion of crystal regrowth, increased activation, and crystal quality at various temperatures. Shallow, lower dose implants are capable of single crystal regrowth, producing high levels of activation >1 × 1020 cm−2 and nominal mobilities for highly arsenic-doped silicon. However, higher energy implants that fully amorphize the film regrow polycrystalline silicon with low mobilities even at very high temperatures (1250 °C), unsuitable for source–drain formation in logic devices.

In-Line-Test of Variability and Bit-Error-Rate of HfOx-Based Resistive Memory

Spatial and temporal variability of HfOx-based resistive random access memory (RRAM) are investigated for manufacturing and product designs. Manufacturing variability is characterized at different levels including lots, wafers, and chips. Bit-error-rate (BER) is proposed as a holistic parameter for the write cycle resistance statistics. Using the electrical in-line-test cycle data, a method is developed to derive BERs as functions of the design margin, to provide guidance for technology evaluation and product design. The proposed BER calculation can also be used in the off-line bench test and build-in-self-test (BIST) for adaptive error correction and for the other types of random access memories.

Application of cluster Ion (carbon) implantation for strain applications

For 28nm and beyond technology nodes it is essential to enhance carrier mobility of the devices by introducing embedded Si:C structures using new materials or structures or new implant and anneal process schemes. In this article we review and verify available information using Si:C formation through implant and anneal approach with low temperature cluster carbon and cluster phosphorous implants. We show here the difference in process results for single and double carbon implants for various pre-anneal and laser annealing conditions. This article explores the effect of cluster carbon implants on various pre-anneal conditions and implant temperature effects on sheet resistance, carbon substitution and junction depths which are critical in determining important device characteristics.

Strained Si:C using low temperature clustercarbon implants and laser annealing

It is shown that Cluster Carbon implantation can be an effective process for making Si:C stressor layer, particularly due to the self-amorphization feature of cluster implantation. Carbon incorporation challenges the formation of NMOS junction structures due to the competition between carbon and dopant atoms to occupy the Si lattice sites and also excess carbon causes serious deactivation of the dopant species. This work now extends to show the effect of low temperature multiple carbon implants and laser annealing on sheet resistance (Rs), carbon substituitionality ([C]subs) and re-crystallization of Si:C layer. The results show that sheet resistance is lower for room temperature implants when compared to cold implants for any anneal condition and but the carbon substitution is slightly higher at low temperature cases. Good recrystallization with no visible defects as seen through XTEM images were observed for both RT and cold implant cases for spike annealed cases. For low temperature RTA anneals, cold i...

Characterization of sub-nm AlO x and LaO x capping layers on high-k gate stack film systems using VuV (λ=120 nm) reflectivity

This paper details the use of vacuum ultraviolet (120 nm < λ < 800 nm) spectroscopic reflectivity to simultaneously measure AlOx and LaOx capping layers and the underlying high-k film stack system. It is demonstrated that the sensitivity of the method originates in the VuV portion of the spectra where absorption of these materials contributes significantly to the overall optical response. As a result, the reflectivity in the VuV region accurately resolves sub-nm changes in these capping layer thicknesses, while data in the Vis-uV (190 < λ < 800 nm) wavelengths show negligible differences. The extracted physical thicknesses are shown to trend consistently with the EOT and Vfb data from identically prepared MOSCAP samples, thus highlighting this method as a suitable candidate for in-line metrology of sub-nm capping layers on high-k film stacks.