K.-W. Ang

300mm FinFET results utilizing conformal, damage free, ultra shallow junctions (X j ∼5nm) formed with molecular monolayer doping technique

We demonstrate for the first time, a 20nm FinFET using a new, conformal, and damage-free monolayer doping technique. Unlike conventional ion-implantation, this approach makes use of a dopant-containing precursor to uniformly assemble a monolayer of covalently bonded dopants to enable an ultra-shallow (Xj∼5nm) and abrupt (0.6nm/dec) junction formation around a high aspect ratio fin structure, which overcomes the possible FinFET pitch scaling limitations of traditional doping techniques. FinFETs featuring MLD junctions were successfully demonstrated with good electrostatics control down to a gate length of ∼40nm. With further scaling of the fin width, sub-threshold swing and threshold voltage roll-off can be further improved. This low damage and conformal doping is a promising technique to address key FinFET scaling issues associated with parasitic series resistance and short channel control for the 15nm node and beyond.

FinFET parasitic resistance reduction by segregating shallow Sb, Ge and As implants at the silicide interface

This paper reports a new contact technology comprising antimony (Sb) co-implantation and segregation to reduce Schottky barrier height (SBH) and parasitic series resistance for N-FinFETs. Experiments with shallow Sb, Ge and As co-implantation in the source/drain (S/D) regions of SOI FinFET found that all three implant species significantly reduced extrinsic resistance. The Sb implant with a 5e13 cm-2 dose produced the best result with a 31% reduction of extrinsic resistance and a corresponding Ion increase of 19%. This optimum Sb implant is shown to reduce specific contact resistivity (ρc) below 10-8Ω-cm2 by decreasing the SBH and increasing the barrier steepness. Electrostatic control comparable to the reference device indicates no degradation in short channel effects for either Sb, Ge or As. This low ρc is promising to address key FinFET scaling issues associated with parasitic series resistance for the 14nm node and beyond.

New insights into SILC-based life time extraction

The breakdown (TDDB/SILC) characteristics of nMOS transistors with hafnium-based gate dielectric stacks of various zirconium content were investigated. It is found that the gate stack composition affects the SILC-voltage dependency while the voltage value chosen for SILC monitoring impacts significantly the SILC-based lifetime projection. For the worst case lifetime evaluation, SILC should be monitored at its maximum value rather than at any pre-defined, fixed voltage.

Performance and variability in multi-V T FinFETs using fin doping

The impact of fin doping (B, P, As) on FinFET device parameters is studied for high-K/midgap metal gate SOI FinFETs. For a fin width of ~25 nm, >;1 V VT modulation is demonstrated from accumulation mode (AM) to inversion mode (IM). IM FinFETs improve short channel FinFET electrostatics, on-off ratio, and VT variability compared to their undoped counterparts. The same parameters degrade in accumulation mode FinFETs. A VT modulation of ±0.25 V using fin B and P doping comes at the expense of 24% and 14% high field mobility penalty for NFET and PFET, respectively. For the same dose, Arsenic is found to modulate the VT more effectively than does Phosphorus. Basic modeling results show that for aggressively scaled (5 nm-wide) fins, the impact of single dopant atom on VT can be as high as 25 mV, severely challenging the viability of the technique towards the end of roadmap.

Impact of NiPt Thickness Scaling on Contact Resistance From Thin-Body FD SOI to Trigate FETs

The impact of NiPt thickness scaling on total resistance is investigated using short-channel (Lg = 40 nm) nm high-k metal-gate complementary SOI MOSFETs with fin widths varying from 500 nm (planar single-gate thin-body FD SOI FET) to 25 nm (trigate FET). It is shown that limiting the amount of NiPt available for silicidation becomes increasingly critical as fin width scales due to a reduced silicide-to-silicon interfacial contact area and facilitated silicide encroachment toward the channel. The prevention of Schottky contact by scaling NiPt thickness from 10 to 5 nm on a 20-nm-thick SOI enabled a >; 2 × (NFET) and >; 6 × (PFET) reduction in total resistance along with swing and DIBL improvements on trigate FETs.

Conformal, low-damage shallow junction technology (Xj∼5nm) with optimized contacts for FinFETs as a Solution Beyond 14nm Node

A new conformal and damage free doping technique (monolayer doping, MLD) has been demonstrated on FinFETs with good control of short channel effects down to a gate length of ~40nm and 20nm of Wfin. Unlike conventional ion-implantation, this approach makes use of a dopant-containing precursor to uniformly assemble a monolayer of covalently bonded dopants to enable ultra-shallow junction (USJ) of ~5nm, showing great potential for FinFET junction scaling. This low damage, conformal doping technique is promising to address key FinFET scaling issues: series resistance and short channel control for 14nm node and beyond. A sub-5nm junction depth with a steep junction abruptness has been successfully achieved on 300mm platform.

Challenges of III–V materials in advanced CMOS logic

The superior transport properties of III-V materials are promising candidates to achieve improved performance at low power. This paper examines the module challenges of III-V materials in advanced CMOS at or beyond the 10 nm technology node, and reports VLSI compatible epi, junction, contact and gate stack process modules with Xj<;60;10nm, N_D=5×10¹⁹ cm^-3, ρ_c= 6Ω.μm² and Dit = 4×10¹² eV^-1 cm^-2. Si VLSI fab and ESH protocols have been developed to enable advanced process flows.

PBTI improvement in gate last HfO 2 gate dielectric nMOSFET due to Zr incorporation

PBTI in the HfxZryO gate dielectric low temperature full gate last process flow nMOSFETs was demonstrated to be reduced compared to the HfO2 gate dielectric devices of a similar EOT. PBTI degradation in both stacks was successfully modeled within a common framework of fast and slow electron trapping components in the gate dielectrics. The fast component was assigned to the resonance electron trapping in the pre-existing high-κ dielectric defects while a slow, temperature dependent component could be attributed to the migration of the trapped electrons to unoccupied defect sites. Lower PBTI degradation in the Zr:HfO2 stack was shown to be caused by a smaller fast electron trapping component.

Simple FinFET gate doping technique for dipole-engineered Vt tuning and CET scaling

In this paper, we report a Vt tuning technique by dipole-engineering dopant incorporation in the FinFET metal gate stack. Remote interfacial layer scavenging induced by the metal gate dopants has an added advantage of improving the CET, without impacting short channel behavior. Using Al as the dipole-inducing dopant in a FinFET gate stack, a 170mV of positive Vt shift with 0.8Å CETinv reduction was demonstrated. Dopant profiles can be tailored to simply render a CET reduction alone without any Vt tuning, if needed. These results demonstrate key progress towards realizing multi Vt FinFET device architectures for 20nm node and beyond.

Performance and reliability investigation of (110) and (100) sidewall oriented MugFETs

In order to continue technology scaling to meet future performance needs, multi-gate field effect transistors (MugFETs), are currently under investigation. MugFETs can be fabricated on silicon-on-insulator (SOI), and they are especially attractive because their three-dimensional structure enables excellent immunity to short channel effects, without significant changes to conventional CMOS fabrication techniques. One MugFET design of interest is known as the FinFET, where a hard mask is placed on the top surface of a fin structure to decouple it from the sidewall device operation (fig. 1). FinFETs can be fabricated with either the (110) sidewall surface or (100) sidewall where the crystal orientation of the fin sidewalls can have an impact on mobility and thereby provide a mobility boost based on orientation (fig. 1) [1,2]. In planar CMOS technologies, orientation dependent mobility enhancement has been demonstrated through the use of hybrid orientation technology (HOT) [3,4]. Here, hole (h+) mobility (μeff) increases significantly when the channel orientation changed from Si(100) to Si(110). However, the electron (e−) mobility is severely degraded with the same orientation change. Therefore, there arises a need for HOT to take advantage of h+ μeff on Si(110) and e− μeff on Si(100). Our work demonstrates that the nMOS FinFET devices actually are not as severely degraded as planar nMOS, thereby mitigating the need to have orientation dependent CMOS FinFETs for μeff enhancement (fig. 2) [5]. However, a correlation of long channel mobility to short channel performance is necessary to confirm similar performance characteristics (fig. 3). Moreover, the implications of sidewall surface orientation on reliability issues such as hot carriers [6,7] and bias temperature instability [8,9] also need to be addressed. The surface orientation or fin structure may be more susceptible to degradation during stress. Possible causes include: Si interface bonds available for bond breakage [10] in the (110) plane, or structural properties that impact reliability differently than planar devices. In this work, we evaluate the dependence of FinFET sidewall orientation on performance (i.e., mobility and Ion/Ioff) and reliability, where hot carrier injection and BTI are evaluated.