Raj Jammy

Si tunnel transistors with a novel silicided source and 46mV/dec swing

We report a novel tunneling field effect transistor (TFET) fabricated with a high-k/metal gate stack and using nickel silicide to create a special field-enhancing geometry and a high dopant density by dopant segregation. It produces steep subthreshold swing (SS) of 46mV/dec and high ION/IOFF ratio (∼108) and the experiment was successfully repeated after two months. Its superior operation is explained through simulation. For the first time convincing statistical evidence of sub-60mV/dec SS is presented. More than 30% of the devices show sub-60mV/dec SS after systemic data quality checks that screen out unreliable data.

Work function engineering using lanthanum oxide interfacial layers

A La2O3 capping scheme has been developed to obtain n-type band-edge metal gates on Hf-based gate dielectrics. The viability of the technique is demonstrated using multiple metal gates that normally show midgap work function when deposited directly on HfSiO. The technique involves depositing a thin interfacial of La2O3 on a Hf-based gate dielectric prior to metal gate deposition. This process preserves the excellent device characteristic of Hf-based dielectrics, but also allows the realization of band-edge metal gates. The effectiveness of the technique is demonstrated by fabricating fully functional transistor devices. A model is proposed to explain the effect of La2O3 capping on metal gate work function.

Prospect of tunneling green transistor for 0.1V CMOS

Well designed tunneling green transistor may enable future VLSIs operating at 0.1V. Sub-60mV/decade characteristics have been convincingly demonstrated on 8″ wafers. Large ION at low VDD are possible according to TCAD simulations but awaits verification. VDD scaling will greatly benefit from low (effective) band gap energy, which may be provided by type II heterojunctions of Si/Ge or compound semiconductors.

Chemical analysis of HfO2∕Si (100) film systems exposed to NH3 thermal processing

Nitrogen incorporation in HfO2∕SiO2 films utilized as high-k gate dielectric layers in advanced metal-oxide-semiconductor field effect transistors has been investigated. Thin HfO2 blanket films deposited by atomic layer deposition on either SiO2 or NH3 treated Si (100) substrates have been subjected to NH3 and N2 anneal processing. Several high resolution techniques including electron microscopy with electron energy loss spectra, grazing incidence x-ray diffraction, and synchrotron x-ray photoelectron spectroscopy have been utilized to elucidate chemical composition and crystalline structure differences between samples annealed in NH3 and N2 ambients as a function of temperature. Depth profiling of core level binding energy spectra has been obtained by using variable kinetic energy x-ray photoelectron spectroscopy with tunable photon energy. An “interface effect” characterized by a shift of the Si4+ feature to lower binding energy at the HfO2∕SiO2 interface has been detected in the Si 1s spectra; however,...

Improved Electrical Characteristics of Ge-on-Si Field-Effect Transistors With Controlled Ge Epitaxial Layer Thickness on Si Substrates

The authors report on the novel MOSFETs that were fabricated on thin relaxed Ge epitaxial layers grown on Si substrates. With controlled epi-Ge thickness, selectively activated shallow source/drain (S/D) junctions are formed using low dopant activation energy of Ge. The Ge epitaxial layers determine the effective S/D junction depth by selectively activating S/D implantations only in the Ge layers, while suppressing activation in the Si substrates. Low junction leakage current and capacitance are also achieved by forming S/D junctions in Si substrates as well as in Ge layers with controlled epi-Ge thickness. With this technique applied to Ge-on-Si epitaxial layers, Ge pMOSFETs showed an improvement in short channel effects and junction characteristics.

Improved Ge Surface Passivation With Ultrathin

To realize high-mobility surface channel pMOSFETs on Ge, a 1.6-nm-thick SiO_X passivation layer between the bulk Ge substrate and HfSiO gate dielectric was introduced. This approach provides a simple alternative to epitaxial Si deposition followed by selective oxidation and leads to one of the highest peak hole mobilities reported for unstrained surface channel pMOSFETs on Ge: 332 cm²middotV^-1middots^-1 at 0.05 MV/cm-a 2times enhancement over the universal Si/SiO₂ mobility. The devices show well-behaved output and transfer characteristics, an equivalent oxide thickness of 1.85 nm and an I_ON/I_OFF ratio of 3times10³ without detectable fast transient charging. The high hole mobility of these devices is attributed to adequate passivation of the Ge surface

\hbox{SiO}_{X}

Atomic layer deposited HfO2 films on Si(100) substrates have been measured by extended x-ray absorption fine-structure (EXAFS), pre- and postanneal processing. Analysis of the second coordination shell indicates an increase in atomic order with increasing film thickness for each anneal temperature and with increasing anneal temperature for each film thickness. Fourier transformed EXAFS spectra fit with HfO2 reference phases have identified orthorhombic to tetragonal to monoclinic transformations. Evidence for greater retention of the higher permittivity metastable tetragonal phase corresponding to thinner HfO2 films is consistent with a surface energy effect giving rise to the critical grain size phenomenon.

Enabling High-Mobility Surface Channel pMOSFETs Featuring a HfSiO/WN Gate Stack

In this letter, we propose the design and simulation study of a novel transistor, called HFinFET, which is a hybrid of an HEMT and a FinFET, to obtain excellent performance and good off-state control. Followed by the description of the design, 3-D device simulation has been performed to predict the characteristics of the device. The device has been benchmarked against published state of the art HEMT as well as planar and nonplanar Si n-MOSFET data of comparable gate length using standard benchmarking techniques.

Characterizing crystalline polymorph transitions in HfO2 by extended x-ray absorption fine-structure spectroscopy

Recent experiments have demonstrated the ability to alleviate Fermi-level pinning, resulting in reduced Schottky barrier heights (SBHs) and reduced contact resistivity by inserting thin layers of dielectric at the contact interface. In this letter, FinFETs with dielectric SBH tuning layers are investigated and shown to have reduced contact resistance over the control wafer. The reduced contact resistivity results in an ≈25% increase in drive current as well as a reduction of RS/D by 100 Ω · μm. Contact chain measurement shows a 10-Ω · μm2 reduction in specific contact resistivity over the control wafer associated with a 100-meV reduction in SBH. Routes to further improvements in device performance are discussed, including key material considerations for dielectric tuning layers.

HFinFET: A Scalable, High Performance, Low Leakage Hybrid n-Channel FET

The authors report on the thermal stability of Ge metal-oxide-semiconductor (MOS) devices. Ge MOS capacitors with ZrO2 high-k gate dielectric and TaN metal gates were fabricated on Ge epitaxial films. Ge MOS capacitors exhibited a very low gate leakage current density of ∼1×10−6A∕cm2 with a capacitance equivalent thickness of 13A. The excellent electrical characteristics, however, degraded when Ge∕ZrO2 gate stacks were subsequently annealed at elevated temperatures that are potentially used for transistor fabrication. The thermal degradation was due primarily to the formation of interfacial Ge oxides. Ge oxidation temperature was identified using surface analysis and correlated with electrical characteristics.