Martin Stiftinger

Flash-based Field Programmable Gate Array Technology with Deep Trench Isolation

A highly scalable flash-based Field Programmable Gate Array (FPGA) technology has been achieved with Deep Trench Isolation (DTI). The DTI allows for a reduced cell size and enables Independent Pwell (IPW) operation. The IPW allows the Fowler-Nordheim (FN) Uniform Channel Program and Erase (UCPE) with less than plusmn10 V. Additionally, the IPW approach allows a greater flexibility in the array bias scheme reducing the gate disturb during programming and eliminating all Gate-Induced Drain Leakage (GIDL) conditions. Characterization of a FPGA cell and 0.5 Mbit array with 90 nm design rules is demonstrated with excellent electrical characteristics.

Highly Scalable Embedded Flash Memory With Deep Trench Isolation and Novel Buried Bitline Integration for the 90-nm Node and Beyond

In this paper, we embedded a Flash memory cell with 90-nm ground-rules in a high-performance CMOS logic process. A novel deep trench isolation (DTI) module enables an isolated p-well (IPW) bias scheme, leading to Flash with uniform channel program/erase by Fowler-Nordheim tunneling without gate induced drain leakage, a key feature for low-power portable electronics. The IPW concept leads to a compact cell design and a highly scalable high-voltage periphery through the narrow intrawell and interwell isolation spaces. The memory arrays are defined by DTI of each bitline (BL) from its neighboring BLs. We additionally present a buried BL (BBL) concept that links the source contacts of each individual BL via the IPW; thus, effectively eliminating one metal line per BL and reducing overall cell size. A conservative cell size shrink of about 40% can be achieved for a uniform channel program/erase-Flash cell with deep trench and BBL compared to a conventional 21F2cell.

Slope only sense amplifier with 4.5ns sense delay for 8Mbit memory sector, employing in situ current monitoring with 66% write speed improvement in 40nm embedded flash for automotive

This paper proposes two new design techniques, the slope sense amplifier (S-SA) circuit combined with in situ current monitoring (ISCM) implemented in a 40nm embedded FLASH technology. S-SA reduces the sense delay time below 4.5ns thereby enabling a sub 10ns read access time operation for an 8Mbit memory sector. It also provides a power reduction of more than 40% and reduces the occupied area of the sensing circuits by 50%. The S-SA enables a reduced signal development time on the BL increases the read window by 50%. In addition the ISCM improves the write performance by a factor of at least 1.6.