Snezana Jenei

High Q inductor add-on module in thick Cu/SiLK/sup TM/ single damascene

Thick Cu single damascene inductors with very high Q factors are integrated on top of a standard aluminum 3LM BEOL process. Obtained Q factors are more than four times higher than Q factors of the inductors of the same geometry processed in the Al 3LM BEOL. For an inductor of 2.8 nH inductance, a Q peak of 24 at 2 GHz was reached by using 4 /spl mu/m thick Cu on a 2 /spl mu/m IMD oxide layer.

Physics-based closed-form inductance expression for compact modeling of integrated spiral inductors

A closed-form inductance expression for compact modeling of integrated inductors is presented. The expression is more accurate than previously published closed formulas. Moreover, due to its physics-based nature, it is scalable. That is demonstrated by comparison with the measured inductance for a complete set of inductors with different layout parameters.

Investigation of PECVD dielectrics for nondispersive metal-insulator-metal capacitors

Metal-insulator-metal (MIM) capacitors with PECVD nitride exhibit trap-induced dispersive behavior, which leads to degradation in capacitor linearity at low frequencies, limiting the accuracy in precision analog circuits. While LPCVD oxide results in nondispersive behavior, the high deposition temperature excludes the use of LPCVD dielectrics for MIM capacitors using the standard back-end metal layers as capacitor bottom plates. The latter is preferred in view of the low substrate coupling needed for RF applications. In this work, alternative PECVD dielectrics have been investigated with respect to frequency dependence of voltage linearity, hysteresis, matching, and leakage characteristics. It will be shown that ONO stacks offer a combination of good voltage linearity, absence of dispersive behavior and hysteresis, excellent matching, and low leakage.

A 5 GHz fully integrated ESD-protected low-noise amplifier in 90 nm RF CMOS

A 5.5 GHz fully integrated low-power ESD-protected low-noise amplifier (LNA), designed and verified in a 90 nm RF CMOS technology, is presented for the first time. This 9.7 mW LNA features a 13.3 dB power gain with a noise figure of 2.9 dB, while maintaining an input return loss of -14 dB.

Low-power voltage-controlled oscillators in 90-nm CMOS using high-quality thin-film postprocessed inductors

Wafer-level packaging (WLP) technology offers novel opportunities for the realization of high-quality on-chip passives needed in RF front-ends. This paper demonstrates a thin-film WLP technology on top of a 90-nm RF CMOS process with one 15-GHz and two low-power 5-GHz voltage-controlled oscillators (VCOs) using a high-quality WLP or above-IC inductor. The 5-GHz VCOs have a power consumption of 0.33 mW and a phase noise of -115 dBc/Hz and -111 dBc/Hz at 1-MHz offset, respectively, and the 15-GHz VCO has a phase noise of -105 dBc/Hz at 1-MHz offset with a power consumption of 2.76 mW.

A 0.35 /spl mu/m SiGe BiCMOS process featuring a 80 GHz f/sub max/ HBT and integrated high-Q RF passive components

A SiGe HBT, fabricated by means of selective epitaxy, and high-Q RF passive components have been integrated into a 0.35 /spl mu/m BiCMOS process. The HBT features an f/sub T/ of 50 GHz and f/sub max/ of 80 GHz at V/sub BC/=2 V. The npn transistors are integrated in a 0.35 /spl mu/m CMOS process with poly resistors, MIM capacitors and thick metal 4 on chip spiral inductors.

High Q inductors and capacitors on Si substrate

In this paper, the impact of conventional silicon technology parameters on the characteristics of passives is studied. For both inductors and capacitors, cost-effective modules, which integrate easily into wiring BEOL (back-end of line) in a conventional silicon technology and provide high Q factor components are presented. For an inductor of 3 nH, designed for 2 GHz frequency applications, and fabricated in thick Cu as an add-on module, Q factor of /spl sim/24 is reached. The metal insulator metal (MIM) capacitor module with outstanding RF performances and a Q factor ranging from 100-1000 in the few GHz frequency range is developed in the Al BEOL. Compact lumped element SPICE models for both components are proposed and verified.

Add-on Cu/SiLK/sup TM/ module for high Q inductors

Thick Cu single damascene inductors are integrated on top of a standard aluminum three-levels-of-metal (3LM) back-end of line (BEOL) silicon process. The obtained Q factors are more than four times higher than Q factors of the inductors of the same geometry processed in the Al 3LM BEOL. For an inductor of 3 nH designed for 2-GHz frequency applications and fabricated in thick Cu/SiLK/sup TM1/ as an add-on module, a Q factor of /spl sim/24 is reached. A compact two-section lumped element SPICE model is proposed and validated for both inductors in thick Cu/SiLK/sup TM/ and inductors in standard aluminum 3LM BEOL.

Impact of scaling on analog/RF CMOS performance

Analog/RF CMOS design in deep-sub micron digital CMOS is particularly challenging due to conflicting device performance requirements. The continuous scaling of digital CMOS has resulted in cut-off frequencies (f/sub T/) above 100Hz. however this improvement comes at a cost of degraded output resistance and reduced intrinsic gain. The difficulty of integrating analog/RF and high-performance digital functions on a single chip are expected to increase with scaling. In particular, it becomes a major issue to maintain analog performance parameters like 1/f noise and matching together with new high-k gate dielectrics. A lower nominal supply voltage is clearly beneficial for designers of digital circuits (lower power consumption, higher speed), but it presents difficult challenges for their analog designer peers. This review article discusses a number of significant items for analog designs in present and future CMOS processes and possible ways to maintain/improve their analog/RF performances. We illustrate the current achievements on a 90 nm CMOS technology and give an overview of the different options opened for future technologies.

Wafer-level packaging technology for extended global wiring and inductors

Wafer level packaging (WLP) technology, originally introduced for thin film redistribution layers, offers novel opportunities for extended global wiring and passives and has been used to integrate transmission lines and state-of-the-art high Q on-chip inductors on top of a five-levels-of-metal (5 ML) Cu/oxide back-end of line (BEOL) 20/spl Omega/cm silicon process. The transmission lines and inductors are realized above the passivation using thick post-processed dielectric (BCB, /spl epsiv//sub r/=2.65) and Cu layers. Measurements on the BEOL before and after post-processing show no significant shifts for all 5 metal layers. Post-processed 50/spl Omega/ transmission lines. have losses below -0.1dB/mm@25GHz; a InH inductor has a peak Q-factor of 38 at 4.7GHz with resonance frequency (F/sub res/) of 29GHz, the Q-factor tops 30 over 2.6-8.6GHz. Patterned polysilicon ground shields further improve the performance: a Q-factor increase of 90% was demonstrated at 7GHz for a 2.25nH inductor.