Uwe Hodel

RF ESD protection strategies: Codesign vs. low-C protection

The present work is focussed on the trade off between conventional RF ESD protection concepts optimized in terms of capacitive load and the frequently discussed RF ESD codesign idea with ESD protection skilfully integrated into RF circuit design. A narrow and a broadband RF test circuit were developed to put the benchmark on a firm basis. RF and ESD experiments are discussed, showing where the higher effort for the codesign approach starts to pay off.

A digitally controlled DC-DC converter for SoC in 28nm CMOS

Battery operation in mobile applications needs power efficient DC-DC converters which are able to handle battery voltages up to 5.5V. Normally, these DC-DC converters are built in special technologies. For decreased footprint and chip count of the overall system, a system-on-chip solution on modern CMOS technology with core supply voltages around 1V is preferred. The presented DC-DC buck converter generates 0.9 to 1.8V at output currents up to 500mA from a battery voltage of 2.4 to 5.5V with high efficiency in a high-k 28nm metal-gate CMOS technology.

A 31-dBm, high ruggedness power amplifier in 65-nm standard CMOS with high-efficiency stacked-cascode stages

A novel, high ruggedness power amplifier topology in a 65-nm CMOS technology is proposed. The proposed stacked cascode topology uses only standard devices available in a modern triple-well CMOS process to achieve breakdown voltages of more than 18V. The power amplifier stage delivers 28 dBm output power at a power-added efficiency (PAE) of 69.9% from a 3.6V supply. The saturation gain is 18 dB. A watt-level power amplifier for GSM low-band operation with 31-dBm output power and 61% PAE is presented.