Martin Wendel

Harnessing the base-pushout effect for ESD protection in bipolar and BiCMOS technologies ☆

In an ESD analysis of the radio frequency (RF) npn transistor in three BiCMOS generations the basepushout effect is identified as a dominant factor, causing a characteristically high differential resistance at low and intermediate ESD currents and a second non-thermal snapback leading to the transistors usual low-ohmic breakdown mode. Concepts to exploit the base-pushout effect for improved RF ESD protection schemes are presented.

A self protecting RF output with 2 kV HBM hardness

The present work focuses on the ESD protection of an RF output stage which consists of a fully silicided NMOS stack of mixed device type in a 2.8 V domain. The application of co-design measures improves the ESD hardness from 250 V to 2 kV HBM.

Advanced 2D/3D ESD device simulation – a powerful tool already used in a pre-Si phase

The tremendous advantages of adequate 2D/3D device simulations for ESD optimization are demonstrated. The pre-silicon ESD-protection concept of a new CMOS technology was completely based on high-current I-V characteristics simulated for different NMOS variations. Silicon verification proved the excellent simulation quality of the electrical behavior and, furthermore, of ESD thresholds.

ESD failure caused by parasitic SCR in an overvoltage tolerant I/O

A new type of ESD failure in an overvoltage tolerant I/O of a CMOS embedded flash technology is presented. The failure is caused by the triggering of a parasitic SCR formed by high voltage devices between I/O and supply. Several solutions to prevent the failure are shown.