Thomas Schafbauer

A 0.13 /spl mu/m CMOS platform with Cu/low-k interconnects for system on chip applications

We describe an advanced 0.13 /spl mu/m CMOS technology platform optimized for density, performance, low power and analog/mixed signal applications. Up to 8 levels of copper interconnect with the industrys first true low-k dielectric (SiLK, k=2.7) (Goldblatt et al., 2000) result in superior interconnect performance at aggressive pitches. A 2.28 /spl mu/m/sup 2/ SRAM cell is manufactured with high yield by introducing elongated local interconnects on the contact level without increasing process complexity. Trench based embedded DRAM is offered for large area memory. Modular analog devices as well as passive components like resistors, MIM capacitors and intrinsic inductors are integrated.

High performance 50 nm CMOS devices for microprocessor and embedded processor core applications

50 nm CMOS transistors for high performance and low active power applications are presented. Good short-channel effect control is achieved down to 35 nm gate length. These transistors will be incorporated in a leading edge 100 nm technology, with optimized triple well, nitrided oxide gate dielectrics, 193-nm lithography, 9-level hierarchical Cu interconnects, and low-k dielectrics. These high performance transistors have the best current drive at a given leakage current reported in the literature.

Scalability and biasing strategy for CMOS with active well bias

We analyze the scalability of the two well bias strategies: reverse bias to reduce standby power, and forward bias to improve the speed or to reduce active power. We then present the device design space that includes well bias as an integral part of the design variables following the SIA Roadmap specifications. We show that proper well biases are needed for bulk CMOS just to continue to meet the SIA Roadmap requirements for performance and standby current. The scalabilities for forward bias and reverse bias are different. The advantage of reverse bias is diminishing with scaling due to low initial V/sub t/ values, short-channel effects, and band-to-band tunneling. The advantage of the forward body bias is preserved better with scaling due to high initial V/sub t/ values as well as smaller depletion width, and increases with V/sub t/ nonscaling. The forward bias approach is not effective in speed improvement for ultra-high performance applications with high V/sub dd/ overdrive and low V/sub t/ to start with, but is effective in active power reduction at a fixed speed target.

Integration of high-performance, low-leakage and mixed signal features into a 100 nm CMOS technology

Low voltage operation in sub-0.25 /spl mu/m requirements mean that the simultaneous integration of all components on a single chip - high performance, low leakage and mixed-signal components - is crucial. In this paper, we present the successful integration of a low leakage gate-dielectric using a triple-gate-oxide process with 16 /spl Aring//24 /spl Aring//52 /spl Aring/ layers, a low-k BEOL and mixed signal components. The 1.5 V SRAM cell with a footprint of 1.26 /spl mu/m/sup 2/ is the smallest 1.5 V cell reported.