MaryJane Brodsky

IrSi1.75 a new semiconductor compound

Optical and Hall effect measurements on thin film layers of polycrystalline IrSi1.75 show that this material is a semiconductor. The band gap is approximately 1.2 eV. The films obtained saturated with silicon were p‐type with a charge carrier density of the order of 4×1017 cm−3.

Influence of preparation conditions on forward‐bias currents of amorphous silicon Schottky diodes

We report on the open‐circuit voltage Voc and the forward‐current–voltage characteristic, J=Js(expqV/nKT−1), of Schottky diodes obtained by evaporation of platinum onto hydrogenated amorphous silicon (a‐Si :H) fabricated by glow‐discharge decomposition of silane. The diode characteristics were studied as a function of several preparation parameters, namely, silane pressure, substrate temperature, silane flow rate, annealing temperature. Rectifying behavior was obtained only for substrate temperatures between 200 and 300°C. Within this constraint, the preparation parameters have only a small effect on Voc but have large influences on n and Js. The factor n decreases towards ideality (n=1) as the silane pressure decreases, as the substrate temperature increases and with annealing of the Pt contact. The corresponding decrease of the concentration of polyhydride H sites with similar variations in the preparation parameters suggests that the recombination center responsible for nonideal value of n are associat...

Thickness dependence of the photoconductivity of phosphorus‐doped hydrogenated amorphous silicon

The thickness and spectral dependences of the photoconductance of phosphorus‐doped hydrogenated amorphous silicon show that the surface and interface layers are more photosensitive than the bulk, and further, that the interface layer is the more photoconductive of the two boundary layers. We interpret the results as further evidence for band bending at the film boundaries.

A novel, low-cost deep trench decoupling capacitor for high-performance, low-power bulk CMOS applications

We present an overview and electrical results for a novel deep trench decoupling capacitor. The process of this decoupling capacitor borrows from the regular embedded DRAM trench process, but with significant process simplification for decoupling use which provide reduced cost and reduced process cycle time. This capacitor can provide significant chip-level area savings, using only 1/8 silicon real estate to fabricate the same capacitance as standard planar gate oxide capacitors. Additionally, the trench decap demonstrates a dramatic improvement in leakage compared to standard planar gate oxide capacitors - as much as 105 improvement in leakage can be realized using trench decaps instead of conventional planar decap designs.

Effect of plasma N2 and thermal NH3 nitridation in HfO2 for ultrathin equivalent oxide thickness

Two methods of HfO2 nitridation including plasma N2 nitridation and thermal NH3 anneal were studied for ultrathin HfO2 gate dielectrics with <1 nm equivalent oxide thickness (EOT). The detailed nitridation mechanism, nitrogen depth profile, and nitrogen behavior during the anneal process were thoroughly investigated by XPS and SIMS analysis for the two types of nitridation processes at different process conditions. Intermediate metastable nitrogen was observed and found to be important during the plasma nitridation process. For thermal NH3 nitridation, pressure was found to be most critical to control the nitrogen profile while process time and temperature produced second order effects. The physical analyses on the impacts of various process conditions are well correlated to the electrical properties of the films, such as leakage current, EOT, mobility, and transistor bias temperature instability.

Reflectivity-induced Variation in Implant Layer Lithography

Scaling of designs to the 45nm and future nodes presents challenges for block level lithography. Shrinking distances between devices drive aggressive resist placement tolerances, challenging the ability to control critical dimension (CD). In particular, the potential variation in shallow trench isolation oxide may result in variation of resist profile and CD, thereby affecting edge placement accuracy. Potential sources of this include wafer-to-wafer or within-wafer STI trench depth variations, and STI CMP variations that may be induced by active area pattern density fluctuations. Some other potential sources of CD fluctuation include oxide sidewall variation, and implant level overlay or CD errors modulating the proximity to the oxide sidewall. Depending on the actual variation of isolation oxide and the exposure latitude of the resist, the CD variations simply from oxide variation may consume a large portion of the CD budget. Several examples are given of variations in resist profile and CD arising from these substrate effects. The CD uniformity of a test structure was shown to decrease dramatically with the addition of a BARC to the resist stack, most likely due to the suppression of substrate reflectivity variations. Simulations performed using Panoramic Technologies software demonstrated the potential sensitivity of the factors outlined above on CD and profile errors. A comparison of simulated vs. experimental results is made for a case of intentional overlay error, showing the failure mode of the resist profile as the mask edge passes from STI to the active area. The simulations using a full physical model provided with the simulation software predict a resist foot forming over the active area, which was confirmed experimentally.

Single wafer cleaning lessons in advanced node gate module development

With single wafer cleaning becoming a mature part of advanced semiconductor manufacturing, it seemed appropriate to reflect on a period of rapid and dramatic change within the gate module. Specifically, there are 6 key learnings that have enabled our team to take embedded contamination from top of the yield pareto to a more baseline level of defectivity. Those key learnings were: 1) Particle removal efficiency is critical. 2) DI Prewet improves pattern fidelity. 3) S/P ratio drives dual gate chemical oxide growth. 4) Hydrophobic dewetting can occur. 5) Predispense sequences are critical. 6) Concentration differences between batch and single wafer tooling can drive significant effects.

Rapid thermal annealing of hydrogenated amorphous silicon grown at low temperature

Hydrogenated amorphous silicon with different levels of phosphorous doping has been deposited by plasma‐enhanced chemical vapor deposition at a temperature of 125 °C. Its electrical properties are largely inferior to those of standard material grown at 275 °C, but they can be improved by a rapid thermal annealing process. The change in electrical conductivity depends on the doping level and is better for 0.1% than 1% or undoped samples. In this case the electrical conductivity, after annealing, increases by three orders of magnitude and is only a factor of 10 less than that of the best conducting material produced at 275 °C. The improvement in electrical properties is not causatively related to the loss of hydrogen. This low‐temperature material, after annealing, forms relatively low resistance contacts with molybdenum or aluminum and is suitable for application in thin‐film transistor technology.

Leveraging puma DF wafer inspection to characterize root cause of yield loss on an advanced 32 nm HKMG SOI technology device

This paper presents a systematic methodology to enable Puma double dark field wafer inspection tool to detect key yield related defect that causes micro-masking defects in the Gate module/sector of an advanced 32nm High-K Metal Gate (HKMG) SOI technology device. Two approaches were adapted to detect the source of the micro-masking defect, namely (i) Patterned wafer inspection in High K metal Gate module to understand the initial findings (ii) Collaborative work with other advanced fabs (Partners) that led to a systematic partitioning approach through the Front End of the Line (FEOL) sectors to exactly pinpoint the root cause of the yield loss in Gate sector. Based on the above systematic partitioning approach, the source of the embedded defect that causes yield loss in gate sector was successfully identified. This methodology has also enabled a process fix to be put in place for reducing the addition of embedded defects in the FEOL sector and has directly helped in improving the yield in FEOL sector. This paper also discusses the advantage of collaborating with different wafer manufacturing companies (IBM partners) in being able to successfully identify root cause of key yield limiting issues.