Shahab Siddiqui

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

Band-gap engineering using SiGe channels to reduce the threshold voltage (VTH) in p-channel MOSFETs has enabled a simplified gate-first high-к/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for SOC applications has unique challenges like the oxidation rate differential with silicon, defectivity and interface state density in the unoptimized state, and concerns with Tinv scalability. In overcoming these challenges, we show that we can leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) HKMG CMOS logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.

Effect of plasma N2 and thermal NH3 nitridation in HfO2 for ultrathin equivalent oxide thickness

Two methods of HfO2 nitridation including plasma N2 nitridation and thermal NH3 anneal were studied for ultrathin HfO2 gate dielectrics with <1 nm equivalent oxide thickness (EOT). The detailed nitridation mechanism, nitrogen depth profile, and nitrogen behavior during the anneal process were thoroughly investigated by XPS and SIMS analysis for the two types of nitridation processes at different process conditions. Intermediate metastable nitrogen was observed and found to be important during the plasma nitridation process. For thermal NH3 nitridation, pressure was found to be most critical to control the nitrogen profile while process time and temperature produced second order effects. The physical analyses on the impacts of various process conditions are well correlated to the electrical properties of the films, such as leakage current, EOT, mobility, and transistor bias temperature instability.

Improving yield through the application of process window OPC

As the industry progresses toward more challenging patterning nodes with tighter error budgets and weaker process windows, it is becoming clear that current single process condition Optical Proximity Corrections (OPC) as well as OPC verification methods such as Optical Rules Checking (ORC) performed at a single process point fail to provide robust solutions through process. Moreover, these techniques can potentially miss catastrophic failures that will negatively impact yield while surely failing to capitalize on every chance to enhance process window. Process-aware OPC and verification algorithms have been developed [1,2] that minimize process variability to enhance yield and assess process robustness, respectively. In this paper we demonstrate the importance of process aware OPC and ORC tools to enable first time right manufacturing solutions, even for technology nodes prior to 45nm such as a 65nm contact level, by identifying critical spots on the layout that became significant yield detractors on the chip but nominal ORC could not catch. Similarly, we will demonstrate the successful application of a process window OPC (PWOPC) algorithm capable of recognizing and correcting for process window systematic variations that threaten the overall RET performance, while maintaining printed contours within the minimum overlay tolerances. Direct comparison of wafer results are presented for two 65nm CA masks, one where conventional nominal OPC was applied and a second one processed with PWOPC. Thorough wafer results will show how our process aware OPC algorithm was able to address and successfully strengthen the lithography performance of those areas in the layout previously identified by PWORC as sensitive to process variations, as well as of isolated and semi-isolated features, for an overall significant yield enhancement.

A novel atomic layer oxidation technique for EOT scaling in gate-last high-к/metal gate CMOS technology

We demonstrated sub-1nm equivalent oxide thickness (EOT) for a gate-last high- к/metal scheme. This is enabled by (1) controllable 1000°C high temperature atomic layer oxidation on a chemical oxide (chemox) to form &#60; 0.5 nm high quality SiO2 interfacial layer (IL); (2) nitrogen profile optimization on post high- к nitridation and anneal. Competitive gate leakage and mobility are achieved at the scaled EOT compared to a chemox IL control (0.2 nm thinner). The physical properties of the gate stack are studied by XPS and SIMS analysis.