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Dive into the research topics where Masaaki Hatano is active.

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Featured researches published by Masaaki Hatano.


international interconnect technology conference | 2002

EM lifetime improvement of Cu damascene interconnects by p-SiC cap layer

Masaaki Hatano; Takamasa Usui; Y. Shimooka; H. Kaneko

Mean time to failure (MTF) of Cu damascene interconnects with p-SiC cap layer is achieved to be approximately 2 times as long as that with conventional p-SiN cap layer. This improvement can be explained by the difference of adhesion between Cu and the cap layer. It is also found that Cu dominant diffusion path is the interface between Cu and the cap layer for Cu interconnects with TaN/Ta and p-SiC, p-SiN.


international interconnect technology conference | 2006

Reliability Improvement by Adopting Ti-barrier Metal B for Porous Low-k IL Structure

Atsuko Sakata; Soichi Yamashita; Seiichi Omoto; Masaaki Hatano; Junichi Wada; Kazuyuki Higashi; Hitomi Yamaguchi; T. Yosho; K. Imamizu; Masaki Yamada; Masahiko Hasunuma; S. Takahashi; A. Yamada; Toshiaki Hasegawa; H. Kaneko

This paper elucidated for the first time that titanium (Ti) is an excellent barrier metal (BM) material from the stand point of cost and performance, especially for the porous low-k ILD materials. Both stress induced voiding (SIV) suppression and one order longer electromigration (EM) lifetime were obtained by introducing Ti instead of the conventional tantalum (Ta). It has been considered that the smaller volume change when oxidized and the existence of metallic Ti-O solid-solution phase for Ti would be the reason for its control of moisture penetration from the low-k ILD materials which resulted in excellent SIV suppression. No electrical resistance increase due to intermetallic reaction between Cu and Ti was observed. Furthermore, the suppression of Cu grain boundary migration was attributed to the segregation of Ti atoms at the Cu grain boundaries. This resulted in higher interconnect reliability


Japanese Journal of Applied Physics | 2004

Electromigration of Al-0.5 wt%Cu with Nb-Based Liner Dual Damascene Interconnects

Takamasa Usui; Tadayoshi Watanabe; Masaaki Hatano; Sachiyo Ito; Junichi Wada; Hisashi Kaneko

The electromigration (EM) of Al-0.5 wt%Cu/Nb-based liner dual damascene (DD) interconnects is investigated for the first time. It is found that EM-induced voids nucleate in the line around the via at the cathode end of the line and their number decreases as the distance from the via becomes longer for the tungusten (W)-single damascene (SD)/aluminum (Al)-dual damascene (DD) interconnects. This fact indicates W-SD/Al-DD interconnects has mono-modal EM failure. Regarding the Al-SD/Al-DD interconnects, two types of layered liner, niobium (Nb)/long throw sputtered (LTS)-niobium nitride (NbN)/Nb and Nb/self ionized sputtered (SIS)-NbN/Nb, are applied and the EM failure mode is investigated. It is found that the Nb/LTS-NbN/Nb liner sample has bi-modal failure, which manifests as normal failure similar to W-SD/Al-DD interconnects and failure with long time to failure (TTF), probably due to the continuous atom flow at the sidewall or bottom of the via in the lower Al-SD interconnects. On the contrary, the Nb/SIS-NbN/Nb liner sample has mono-modal failure with a tight distribution of the EM log-normal distribution, resulting in a high EM reliability.


Archive | 2008

Semiconductor device having oxidized metal film and manufacture method of the same

Atsuko Sakata; Junichi Wada; Seiichi Omoto; Masaaki Hatano; Soichi Yamashita; Kazuyuki Higashi; Naofumi Nakamura; Masaki Yamada; Kazuya Kinoshita; Tomio Katata; Masahiko Hasunuma


Archive | 2010

Method for generating pattern, method for manufacturing semiconductor device, semiconductor device, and computer program

Masaaki Hatano; Motoya Okazaki; Junichi Wada; Takeshi Nishioka; Hisashi Kaneko; Takeshi Fujimaki; Kazuyuki Higashi; Kenji Yoshida; Noriaki Matsunaga


international interconnect technology conference | 2004

Sea of Kelvin multiple-pattern arrangement interconnect characterization for low-k/Cu dual damascene and its findings

Motoya Okazaki; Masaaki Hatano; K. Yoshida; S. Shibasaki; H. Kaneko; T. Yoda; N. Hayasaka


Archive | 2009

Method for fabricating semiconductor device and semiconductor device thereof

Atsuko Sakata; Junichi Wada; Seiichi Omoto; Masaaki Hatano; Soichi Yamashita; Kazuyuki Higashi; Naofumi Nakamura; Masaki Yamada; Kazuya Kinoshita; Tomio Katata; Masahiko Hasunuma


Archive | 2008

Method of forming a multi-level interconnect structure by overlay alignment procedures

Masaaki Hatano


Archive | 2006

Method for generating pattern, method for manufacturing and control semiconductor device, and semiconductor device

Masaaki Hatano; Motoya Okazaki; Junichi Wada; Takeshi Nishioka; Hisashi Kaneko; Takeshi Fujimaki; Kazuyuki Higashi; Kenji Yoshida; Noriaki Matsunaga


Archive | 2003

Halbleitereinrichtung Semiconductor device

Masaaki Hatano; Hiroshi Ikegami; Takamasa Usui; Mie Matsuo

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