Motoya Okazaki

Optimized integrated copper gap-fill approaches for 2x flash devices

Physical vapor deposited (PVD) Cu seed layers have been successfully implemented for Cu gap-fill in feature sizes for the 2x nm flash devices. By tuning the incident angle of the incoming flux of Cu ions as well as utilizing the resputtering parameter, the overhang, sidewall coverage and asymmetry can be well controlled to enable complete fill by subsequent electrochemical deposition (ECD). Chemical vapor deposition (CVD) Cobalt (Co) films were also investigated as an enhancement layer for Cu gap-fill. It was observed that the insertion of a 1.5nm-thick CVD Co layer, deposited between a PVD Ta barrier and a Cu seed layer could effectively enhance gap-fill in the small geometry trench/via structures. The CVD Co enhancement layer could also significantly improve the electromigration (EM) resistance of the Cu interconnects. The Chemical Mechanical Polish (CMP) process was also developed to provide an integrated solution.

Wafer edge polishing process for defect reduction during immersion lithography

The objective of this study was to examine the defect reduction effect of the wafer edge polishing step on the immersion lithography process. The experimental wafers were processed through a typical front end of line device manufacturing process and half of the wafers were processed with the wafer edge polishing just prior to the immersion lithography process. The experimental wafers were then run through two immersion lithography experiments and the defect adders on these wafers were compared and analyzed. The experimental results indicated a strong effect of the edge polishing process on reducing the particle migration from the wafer edge region to the wafer surface during the immersion lithography process.

VOC induced particle generation during wafer transportation and its solution

In this paper, we describe a particle generation issue on 300mm wafers during wafer shipping and transportation while using a FOSB (Front Opening Shipping Box) for the wafer shipping container. The analysis work associated with this defect generation issue and its prevention scheme will also be discussed.

Improvement of Si doping of In 0.53 Ga 0.47 As fin by heated implant

III-V materials are candidates for high mobility channel and low contact resistance SD at 5nm technology node and beyond [1]. Traditional Si+ ion implant of In0.53Ga0.47As at room temperature causes amorphization of fin and formation of stacking fault defects upon activation anneal. We have demonstrated heated implant can eliminate amorphization induced crystalline damages and improve fin conductance.

STT-RAM device performance improvement using CMP process

Current scaling challenges for memory technology have led to fast-paced development of alternative memory technologies. STT-RAM is the leading potential candidate to replace static RAM, dynamic RAM and embedded memory due to its non-volatility, high speed, and unlimited endurance. The performance of STT-MRAM such as memory signal strength (TMR) and data retention (coercivity) is primarily determined by the MTJ film. The deposition of MTJ film requires an underlayer with Angstrom-scale smoothness to achieve good device performance. The Applied Materials Reflexion® LK Prime™ CMP system was used to develop a CMP process to achieve such Angstrom-scale smoothness on the patterned bottom plug-oxide boundary. This degree of smoothness on the bottom plug helped to significantly improve the device performance.

A CMP solution enabling STT-RAM fabrication using via-less process flow

As current memory technologies become difficult to fabricate and scaling presents a growing challenge, R&D in Spin Transfer Torque Random Access Memory (STT-RAM) is growing rapidly. However, the complex stack of STT-RAM memory presents unique processing challenges. One of these is chemical mechanical planarization (CMP) of oxide and nitride for via-less top contacts. Unique materials used in STT-RAM fabrication require a selective and uniform planarization process. We evaluate ceria and silica slurries for this STT-RAM CMP process. Our results show that ceria-based slurry enables oxide-to-tantalum polish rate selectivity exceeding 100:1 and uniform planarization across the wafer. Electrical results of a device fabricated at Applied Materials show tunnel magneto-resistance (TMR) of 143% that is less than 10% degradation than the blanket film TMR.