Kazuyuki Higashi

A manufacturable copper/low-k SiOC/SiCN process technology for 90 nm-node high performance eDRAM

In this paper, we describe the Cu/low-k (k < 3) dual-damascene process integration targeting for 90 nm-node (0.28 /spl mu/m pitch) high performance embedded DRAM devices. A stable and well-controlled dual-damascene structure was realized both by using newly developed stacked mask process (S-MAP) and a low-damage resist ashing process. Problems and solutions for resist poisoning due to the stopper-SiCN layer and capping-SiO/sub 2/ layer are investigated. We also demonstrated a notable via chain yield (with 2.9 M vias) by applying low-k PE-CVD SiOC/SiCN dielectrics.

Reliability Improvement by Adopting Ti-barrier Metal B for Porous Low-k IL Structure

This paper elucidated for the first time that titanium (Ti) is an excellent barrier metal (BM) material from the stand point of cost and performance, especially for the porous low-k ILD materials. Both stress induced voiding (SIV) suppression and one order longer electromigration (EM) lifetime were obtained by introducing Ti instead of the conventional tantalum (Ta). It has been considered that the smaller volume change when oxidized and the existence of metallic Ti-O solid-solution phase for Ti would be the reason for its control of moisture penetration from the low-k ILD materials which resulted in excellent SIV suppression. No electrical resistance increase due to intermetallic reaction between Cu and Ti was observed. Furthermore, the suppression of Cu grain boundary migration was attributed to the segregation of Ti atoms at the Cu grain boundaries. This resulted in higher interconnect reliability

BEOL process integration technology for 45 nm node porous low-k/copper interconnects

Highly reliable BEOL integration technology with porous low-k (k=2.3) was realized by development focusing on plasma damage control and moisture control. A hybrid dielectric scheme with damage resistant porous low-k films and buffer film was applied in view of its inherent advantages for realizing reliable porous low-k integration. A metallization process was developed from the viewpoint of suppressing morphology and adhesion degradation of barrier metal by oxidation. A dummy wiring pattern was also adopted to remove moisture absorbed in porous low-k films. Stress-migration and electromigration satisfying practical reliability were obtained with via size of 75 nm for the first time by utilizing all possible measures for reducing the damage and the moisture.

Highly reliable PVD/ALD/PVD stacked barrier metal structure for 45-nm node copper dual-damascene interconnects

In this paper, we describe highly reliable barrier metal structure for 45nm-node (140nm pitch) high performance copper interconnects. Issues and solutions for utilizing TaN barrier metal by atomic-layer deposition (ALD) process, which is the key technology for scaling down the barrier metal thickness, on low-k ILD materials were investigated. PVD/ALD/PVD stacked barrier metal structure was proposed from the viewpoint of factors affecting reliability such as stress-induced voiding (SiV) and electromigration (EM) endurance, and realized lower wiring resistance than that is attainable with the conventional process. We distinguished the role of each PVD film, and suggest the optimal barrier metal structure to realize highly reliable Cu dual-damascene interconnects.

A fully integrated pillar process for high performance Cu interconnect scheme

A novel back-end of the line process for sub-quarter micron high performance devices, which is called the pillar process, has been proposed. The main features of the process is to form aluminum pillars as via plugs. Compared with the conventional metal plug process, the fine via opening process and complicated cleaning at the via interface are not required. By combining the pillar with a Cu single-damascene process, excellent electrical characteristics such as 20% lower wire resistance and 30% lower via resistance than that of conventional Cu dual-damascene structures have been obtained.

A Study of Water Absorption Induced-Dielectric Constant Increase and Its Suppression on Copper Damascene Interconnect Structure with Porous Low-k (k=2.3) Dielectrics

A key technology for realizing an effective k-value (keff) required for 45nm node is proposed. We studied the behavior of effective dielectric constant derived from capacitance of double-level copper interconnect wires with porous low-k material in detail. The porous low-k materials easily absorb moisture due to process damage and the dielectric constant drastically increases. We have confirmed that if moisture-controlled robust process integration is performed, a reasonably effective dielectric constant (2.8) is obtained corresponding to the ideal bulk k-value (2.4). However, when the sealing of passivation films is broken, the effective dielectric constant increases to the level derived from that of the damaged blanket film. In order to ensure a target capacitance of copper interconnect wire with porous low-k material, it is indispensable to perfectly seal a whole device area from moisture uptake

Plasma process-induced wire-to-wire leakage current for low-k SiOC/Cu damascene structure

The wire-to-wire leakage characteristics were evaluated for SiOC/Cu damascene structure. Our investigation focused on the influence of a trench formation process and the pre-treatment at cap-film deposition which are the main plasma processes in BEOL integration using low-k SiOC films. It became clear that the leakage current is sensitive to ashing conditions at a trench formation step and to cap-film deposition pre-treatment conditions. An optimized plasma process was proposed for Cu/SiOC integration.