Toshiaki Masuhara

A soft error rate model for MOS dynamic RAM's

A soft error rate analysis model for MOS dynamic RAMs is presented. The soft error rate can be quantitatively calculated by using a solution of the equations for diffusion and collection of alpha-particle-induced excess electrons and by combining a statistical treatment of alpha particle energy, incidence angles, and incidence positions with the noise charge calculation. The model is then applied to analyze a soft error experiment on 64-kbit dynamic RAMs. It is shown that soft error characteristics with regard to signal charge (critical charge), as well as alpha energy and incidence angle dependencies, can be definitely determined. The model can also be used to predict the location of soft errors in MOS dynamic RAMs.

A precise MOSFET model for low-voltage circuits

A MOSFET model that is capable of handling the drain current above 10-10A within the temperature range of 220-340 K is proposed. The key feature of the model is that surface potentials at source and pinchoff points are used for the purpose of obtaining a smooth connection between the current solutions in the tail and the saturation regions. Comparison of the model with experiments has been carried out using n-channel MOSFETs with 7 × 1013, 7 × 1014, and 4 × 1015cm-3substrate impurity concentration and 675-, 1470-, and 5030-A gate-oxide thickness. The theoretical calculations are in excellent agreement with the experimental measurements. It is shown that low-level current has a strong influence on the low-voltage static inverter circuit and dynamic memory.

High Packing Density, High Speed CMOS (Hi-CMOS) Device Technology

A new high performance CMOS (Hi-CMOS) technology is developed which provides high packing density, high speed CMOS LSIs. The Hi-CMOS technology utilizes 3 µm photolithographic techniques and device structure dimensions are reduced. In Hi-CMOS devices, n-channel MOS transistors are formed in shallow p-wells and p-channel MOS transistors are formed in shallow n-wells. These double well structures permit independent control of the impurity concentration of both wells. The low concentration wells reduce junction capacitance and the back bias constant. Channel conductances of n-channel and p-channel tansistors increase 30–40% in the Hi-CMOS structures compared with the conventional high concentration well structures. Fabricated Hi-CMOS inverters provide delay times of 0.52 nsec. per stage. This Hi-CMOS technology makes high speed, low power 4 K-bit static RAMs practical.

Laser Diffusion Connection Technology for VLSI Programming

Summary A laser diffusion technology to connect poly-silicon conductors for programming VLSI memories is developed. It is based on the fact that a Nitrogen laser pumped dye laser of 510 nm wavelength irradiated on an intrinsic poly-silicon film in a VLSI, having 10 10 2 resistivity, decreases the film resistivity to 10 3 Ω. The mechanism of resistivity reduction is due to the laser heat diffusion of impurity into the intrinsic poly-silicon film. It is also clarified that the passivation film thick-ness on the intrinsic poly-silicon film changes laser reflectivity from zero to over 50%, affecting the condition of the process. The practical processing condition of laser diffusion connection for VLSI programming to enhance chip yield without damage is obtained.

Soft Error Rate Analysis Model (SERAM) for Dynamic NMOS RAMs

Soft Error Rate Analysis Model (SERAM) for dynamic NMOS RAMs is developed. SERAM simulates the three-dimensional diffusion and collection processes of alpha-particle induced carriers for various incidences. To verify SERAM, the frequency of collected charge in one memory cell and soft error rates of 64 K-bit samples were measured. The simulations were in good agreement with the experiments. Memory cell scaling analysis by SERAM shows that if the cell area scales as (1/K)2, the ratio Qc/Qα decreases as (1/K)β, where K>1, β~0.4 for unsealed voltages, and Qc and Qα are the critical charge and the noise charge, respectively.

Buried J-FET Powered Static RAM Cell

A new high density static RAM cell is designed utilizing a merged junction FET (J-FET) structure. The cell is basically composed of high resistivity-load flipflop and a buried J-FET to supply current to the cell. By eliminating the need for the Al power supply line running through each cell, a smaller-size cell is achieved, i.e. about 900 µm2. To demonstrate the advantages of the new cell, a 2048 word by 8 bit fully static RAM is fabricated with high-performance CMOS (Hi-CMOS) technology. The technology features 3 µm gate length and 4 µm line width. The RAM realizes a typical address access time of 55 ns., and an active power dissipation of 200 mW. The die measures about 26 mm2 and fits into a standard 24 pin package.